AD9981SLASHPCB datasheet(20/44 Pages) AD

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AD9981

Preliminary Technical Data

Rev. 0 | Page 20 of 44

TIMING DIAGRAMS

The following timing diagrams show the operation of the

AD9981.The output data clock signal is created so that its rising

edge always occurs between data transitions and can be used to

latch the output data externally. There is a pipeline in the

AD9981, which must be flushed before valid data becomes

available. This means six data sets are presented before valid

data is available.

tPER

tDCYCLE

tSKEW

DATACK

DATA

HSOUT

Figure 13. Output Timing

DATAIN

P10

P11

HSIN

DATACLK

8 CLOCK CYCLE DELAY

DATAOUT

2 CLOCK CYCLE DELAY

HSOUT

Figure 14. 4:4:4 Timing Mode

DATAIN

P10

P11

HSIN

DATACLK

8 CLOCK CYCLE DELAY

CB/CROUT

YOUT

2 CLOCK CYCLE DELAY

1. PIXEL AFTER HSOUT CORRESONDS TO BLUE INPUT.

2. EVEN NUMBER OF PIXEL DELAY BETWEEN HSOUT AND DATAOUT (6 FOR THE AD9980).

HSOUT

Figure 15. 4:2:2 Timing Mode

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