AD9981SLASHPCB datasheet(14/44 Pages) AD

14 / 44 page

AD9981

Rev. 0 | Page 14 of 44

PIXEL CLOCK

INVALID SAMPLE TIMES

Figure 6. Pixel Sampling Times

Any jitter in the clock reduces the precision with which the

sampling time can be determined and must also be subtracted

from the stable pixel time. Considerable care has been taken in

the design of the AD9981’s clock generation circuit to minimize

jitter. The clock jitter of the AD9981 is 9% or less of the total

pixel time in all operating modes, making the reduction in the

valid sampling time due to jitter negligible.

The PLL characteristics are determined by the loop filter design,

the PLL charge pump current, and the VCO range setting. The

loop filter design is illustrated in Figure 7. Recommended

settings of the VCO range and charge pump current for VESA

standard display modes are listed in Table 9.

8nF

80nF

1.5k

Ω

FILT

PVD

Figure 7. PLL Loop Filter Detail

Four programmable registers are provided to optimize the

performance of the PLL. These registers are

The 12-Bit Divisor Register. The input Hsync frequencies

can accommodate any Hsync as long as the product of the

Hsync and the PLL divisor falls within the operating range

of the VCO. The PLL multiplies the frequency of the Hsync

signal, producing pixel clock frequencies in the range of

10 MHz to 95 MHz. The divisor register controls the exact

multiplication factor. This register may be set to any value

between 2 and 4095 as long as the output frequency is

within range.

The 2-Bit VCO Range Register. To improve the noise

performance of the AD9981, the VCO operating frequency

range is divided into four overlapping regions. The VCO

range register sets this operating range. The frequency

ranges for the four regions are shown in Table 7.

Table 7. VCO Frequency Ranges

PV1

PV0

Pixel Clock

Range (MHz)

KVCO

Gain (MHz/V)

10–21

150

21–42

150

42–84

150

84-95

150

The 3-Bit Charge Pump Current Register. This register

varies the current that drives the low-pass loop filter. The

possible current values are listed in Table 8.

Table 8. Charge Pump Current/Control Bits

Ip2

Ip1

Ip0

Current (µA)

100

150

250

350

500

750

1500

The 5-Bit Phase Adjust Register. The phase of the gen-

erated sampling clock may be shifted to locate an optimum

sampling point within a clock cycle. The phase adjust

Hsync signal with an identical phase shift is available

through the HSOUT pin. Phase adjust is still available if an

external pixel clock is used. The COAST pin or the internal

Coast is used to allow the PLL to continue to run at the

same frequency in the absence of the incoming Hsync

signal or during disturbances in Hsync (such as from

equalization pulses). This may be used during the vertical

sync period or at any other time that the Hsync signal is

unavailable. The polarity of the Coast signal may be set

through the Coast polarity register (Register 0x18,

Bits [6:5]). Also, the polarity of the Hsync signal may

be set through the Hsync polarity register (Register 0x12,

Bits [5:4]). For both Hsync and Coast, a value of 1 is active

high. The internal Coast function is driven off the Vsync

signal, which is typically a time when Hsync signals may be

disrupted with extra equalization pulses.

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