AD9981SLASHPCB datasheet(32/44 Pages) AD

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AD9981

Preliminary Technical Data

Rev. 0 | Page 32 of 44

0x14

Vsync Source

This bit selects the source of the Vsync for sync

processing only if Bit 7 of Register 0x14 is set to 1.

Setting Bit 6 to 0 specifies the Vsync from the input

pin; setting it to 1 selects Vsync from the sync

separator. Power-up default is 0.

Table 22. Active Vsync Select Settings

Select

Result

Vsync input

Vsync from sync separator

0x14

Vsync Input Polarity Override

This bit sets whether the chip selects the Vsync input

polarity or if it is specified. Setting this bit to 0 allows

the chip to automatically select the polarity of the

input Vsync. Setting this bit to 1 indicates that Bit 4 of

is 0.

Table 23. Vsync Input Polarity Override Settings

Override Bit

Result

Vsync polarity determined by chip

Vsync polarity determined by user

0x14

Input Vsync Polarity

If Bit 5 of Register 0x14 is 1, the value of this bit

specifies the polarity of the input Vsync. Setting this

bit to 0 indicates an active low Vsync; setting this bit to

1 indicates an active high Vsync. Power-up default is 1.

Table 24. Vsync Input Polarity Settings

Override Bit

Result

Vsync input polarity is negative

Vsync input polarity is positive

0x14

Vsync Output Polarity

This bit sets the polarity of the Hsync output. Setting

this bit to 0 sets the Hsync output to active low. Setting

this bit to 1 sets the Hsync output to active high.

Power-up default is 1.

Table 25. Vsync Output Polarity Settings

Vsync Output

Polarity Bit

Result

Vsync output polarity is negative

Vsync output polarity is positive

0x14

Vsync Filter Enable

This bit enables the Vsync filter allowing precise

placement of the Vsync with respect to the Hsync

and facilitating the correct operation of the Hsyncs/

Vsync count.

Table 26. Vsync Filter Enable

Vsync Filter Bit

Result

Vsync filter disabled

Vsync filter enabled

0x14

Vsync Duration Enable

This enables the Vsync duration block, which is

designed to be used with the Vsync filter. Setting the

bit to 0 leaves the Vsync output duration unchanged.

Setting the bit to 1 sets the Vsync output duration

based on Register 0x15. Power-up duration is 0.

Table 27. Vsync Duration Enable

Vsync Duration Bit

Result

Vsync output duration is unchanged

Vsync output duration is set by Register

0x15

7:0

Vsync Duration

This is used to set the output duration of the Vsync,

and is designed to be used with the Vsync filter. This is

valid only if Register 0x14, Bit 1 is set to 1. Power-up

default is 10 DDR.

COAST AND CLAMP CONTROLS

0x16

7:0

Precoast

This register allows the internally generated Coast

signal to be applied prior to the Vsync signal. This is

necessary in cases where pre-equalization pulses are

present. The step size for this control is one Hsync

period. For Precoast to work correctly, it is necessary

for the Vsync filter (0x14, Bit 2) and sync processing

filter (Register 0x20, Bit 1) both to be either enabled or

disabled. The power-up default is 00.

0x17

7:0

Postcoast

This register allows the internally generated Coast

signal to be applied following the Vsync signal. This is

necessary in cases where postequalization pulses are

present. The step size for this control is one Hsync

period. For Postcoast to work correctly, it is necessary

for the Vsync filter (0x14, Bit 2) and sync processing

filter (0x20, Bit 1) both to be either enabled or

disabled. The power-up default is 00.

0x18

Coast Source

This bit is used to select the active Coast source. The

choices are the COAST input pin or vsync. If Vsync is

selected, the additional decision of using the VSYNC

input pin or the output from the sync separator needs

to be made (Register 0x14, Bits [7: 6]).

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