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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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CS53L21 数据表(PDF) 48 Page - Cirrus Logic |
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CS53L21 数据表(HTML) 48 Page - Cirrus Logic |
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48 / 66 page  48 DS700PP1 CS53L21 6.8 SPE Control (Address 09h) SPE_ENABLE Default: 0 0 - Reserved 1 - ADC Serial Port to SPE Function: Selects the digital signal source for the SPE. Note: If DIGMIX = 1, SPE_ENABLE must be 1 for the SPE to be functional. Freeze Controls (FREEZE) Default: 0 Function: This function will freeze the previous settings of, and allow modifications to be made to all control port reg- isters without the changes taking effect until the FREEZE is disabled. To have multiple changes in the con- trol port registers take effect simultaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit. 76 543 21 0 Reserved SPE_ENABLE FREEZE Reserved Reserved Reserved SPE_SZC1 SPE_SZC0 |
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