CS53L21 datasheet(25/66 Pages) CIRRUS

25 / 66 page

DS700PP1

CS53L21

4.3.5

Analog Input Multiplexer

A stereo 4-to-1 analog input multiplexer selects between a line-level input source, or a mic-level input

source, depending on the PDN_PGAx and AINx_MUX[1:0] bit settings. Signals may be routed to or by-

passed around the PGA. To conserve power, the PGA’s may be powered down allowing the user to select

from multiple line-level sources and route the stereo signal directly to the ADC. When using the MIC pre-

amp, however, the PGA must be powered up.

Analog input channel B may also be used as an output for the MIC bias voltage. The MICBIAS_SEL bit

routes the bias voltage to either of two pins. The multiplexer must then select from the remainder of the

two input channels.

The ADC, PGA and MIC pre-amplifier each has an associated input resistance. When selecting between

these paths, the input resistance to the A/D will change accordingly. Refer to the input resistance charac-

teristics in the Characteristic and Specification Tables for the input resistance of each path.

4.3.6

MIC & PGA Gain

The MIC-level input passes through a +16 dB or +32 dB analog gain stage prior to the input multiplexer,

allowing it to be used for microphone level signals without the need for any external gain. The PGA must

be powered up when using the MIC pre-amp.

The PGA stage provides an additional +12 dB to -3 dB of analog gain in 0.5 dB steps.

Software

Controls:

“Power Control 1 (Address 02h)” on page 40, “MIC Control (Address 05h)” on page 44 “ADCx

Input Select, Invert & Mute (Address 07h)” on page 47.

Software

Controls:

“Power Control 1 (Address 02h)” on page 40, “ADCx Input Select, Invert & Mute (Address 07h)” on

page 47, “ALCX & PGAX Control: ALCA, PGAA (Address 0Ah) & ALCB, PGAB (Address 0Bh)” on

page 49, “MIC Control (Address 05h)” on page 44.

CS53L21 数据表(PDF) 25 Page - Cirrus Logic