CS53L21 datasheet(22/66 Pages) CIRRUS

22 / 66 page

DS700PP1

CS53L21

4.3

Analog Inputs

AINxA and AINxB are the analog inputs, internally biased to VQ, that accepts line-level and MIC-level sig-

nals, allowing various gain and signal adjustments for each channel.

4.3.1

Digital Code, Offset & DC Measurement

The ADC output data is in two’s complement binary format. For inputs above positive full scale or below

negative full scale, the ADC will output 7FFFFFH or 800000H, respectively and cause the ADC overflow

bit to be set to a ‘1’.

Given the two’s complement format, low-level signals may cause the MSB of the serial data to periodically

toggle between ‘1’ and ‘0’, possibly introducing noise into the system as the bit switches back and forth.

To prevent this phenomena, a constant DC offset is added to the serial data bringing the low-level signal

just above the point at which the MSB would normally toggle, thus reducing the noise introduced. Note

that this offset is not removed (refer to “Analog Characteristics (Commercial - CNZ)” on page 12 and/or

“Analog Characteristics (Automotive - DNZ)” on page 13 for the specified offset level).

The A/D may be used to measure DC voltages by disabling the high-pass filter for the designated channel.

DC levels are measured relative to VQ and will be decoded as positive two’s complement binary numbers

above VQ and negative two’s complement binary numbers below VQ.

Software

Controls:

“Status (Address 20h) (Read Only)” on page 55, “ADC Control (Address 06h)” on page 45.

Multibit

Oversampling

ADC

AIN3A/ MICIN1

MICA_BOOST

Attenuator

ALC

PGAA_VOL[5:0]

ADC_SNGVOL

0/-96dB

1dB steps

ADCA_ATT[7:0]

ADCA_HPF ENABLE

ADCA_HPF FREEZE

PDN_ADCA

ADCA_MUTE

SOFTA

ALC_ENA

ALCB_SRDIS

ALCB_ZCDIS

PDN_MICA

MICBIAS

PDN_MICBIAS

MICBIAS_LVL[1:0]

MICBIAS_SEL

TO SIGNAL PROCESSING

ENGINE (SPE)

INV_ADCA

ALC_ARATE[5:0]

ALC_RRATE[5:0]

MAX[2:0]

MIN[2:0]

ALC_ENB

ALCA_SRDIS

ALCA_ZCDIS

MUX

AIN1A

AIN2A

PGA

+16/

32 dB

AINA_MUX[1:0]

PDN_PGAA

+12/-3dB

0.5dB steps

SOFTA

ZCROSSA

Multibit

Oversampling

ADC

AIN3B/ MICIN2/

MICBIAS

MICB_BOOST

PGAB_VOL[5:0]

ADC_SNGVOL

0/-96dB

1dB steps

ADCB_ATT[7:0]

ADCB_HPF ENABLE

ADCB_HPF FREEZE

PDN_ADCB

ADCB_MUTE

SOFTB

PDN_MICB

INV_ADCB

MUX

AIN1B

AIN2B/MICBIAS

PGA

+16/

32 dB

AINB_MUX[1:0]

PDN_PGAB

+12/-3dB

0.5dB steps

SOFTB

ZCROSSB

Noise Gate NG_ALL

NG_EN

THRESH[3:0]

NGDELAY[1:0]

Attenuator

MUX

MICMIX

MUX

FROM SIGNAL

PROCESSING ENGINE

(SPE)

DIGMIX

+20dB

Digital

Boost

ADCA_DBOOST

+20dB

Digital

Boost

ADCB_DBOOST

Figure 7. Analog Input Architecture

CS53L21 数据表(PDF) 22 Page - Cirrus Logic

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