CS53L21 datasheet(6/66 Pages) CIRRUS

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DS700PP1

CS53L21

1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE

Pin Name

Pin Description

LRCK

Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the

serial audio data line.

SDA/CDIN

(MCLKDIV2)

Serial Control Data (Input/Output) - SDA is a data I/O in I²C Mode. CDIN is the input data line for the

control port interface in SPI Mode.

MCLK Divide by 2 (Input) - Hardware Mode: Divides the MCLK by 2 prior to all internal circuitry.

SCL/CCLK

(I²S/LJ)

Serial Control Port Clock (Input) - Serial clock for the serial control port.

Interface Format Selection (Input) - Hardware Mode: Selects between I²S & Left-Justified interface for-

mats for the ADC.

AD0/CS

(TSTN)

Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode; CS

is the chip-select signal for SPI format.

Test In (Input) - Hardware Mode: This pin is an input used for test purposes only and should be tied to

DGND for normal operation.

VA_PULLUP

Reference Pull-up (Input) - This pin is an input used for test purposes only and must be pulled-up to VA

using a 47 k

Ω resistor.

TSTO

Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con-

nection external to the pin).

AGND

Analog Ground (Input) - Ground reference for the internal analog section.

TSTO

Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con-

nection external to the pin).

CS53L21

SDA/CDIN (MCLKDIV2)

SCL/CCLK (I²S/LJ)

AD0/CS (TSTN)

TSTO

AGND

TSTO

AFILTA

AIN1A

AIN1B

AIN2A

AIN2B/BIAS

MICIN1/AIN3A

MICIN2/BIAS/AIN3B

AFILTB

VA_PULLUP

LRCK

CS53L21 数据表(PDF) 6 Page - Cirrus Logic

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CS53L21 数据表(PDF) 6 Page - Cirrus Logic

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