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CS53L21 数据表(PDF) 28 Page - Cirrus Logic

部件名 CS53L21
功能描述  Low Power, Stereo Analog to Digital Converter
PDF  66 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS53L21 数据表(HTML) 28 Page - Cirrus Logic

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DS700PP1
CS53L21
4.4
Signal Processing Engine
The SPE provides various signal processing functions that apply to the ADC data.
4.4.1
Volume Controls
The digital volume control functions offer independent control over the ADC signal path into the mixer.
The volume controls are programmable to ramp in increments of 0.125 dB at a rate controlled by the soft
ramp/zero cross settings.
The signal paths may also be muted via mute control bits. When enabled, each bit attenuates the signal
to its maximum value. When the mute bit is disabled, the signal returns to the attenuation level set in the
respective volume control register. The attenuation is ramped up and down at the rate specified by the
SPE_SZC[1:0] bits.
4.4.2
Mono Channel Mixer
A channel mixer may be used to create a mix of the left and right channels for the ADC data. This mix
allows the user to produce a MONO signal from a stereo source. The mixer may also be used to imple-
ment a left/right channel swap.
Software
Controls:
“SPE Control (Address 09h)” on page 48
Software
Controls:
“ADCx Mixer Volume Control: ADCA (Address 0Eh) & ADCB (Address 0Fh)” on page 51
Software
Controls:
“Channel Mixer (Address 18h)” on page 51.
VOL
Channel
Swap
+12dB/-51.5dB
0.5dB steps
ADCMIXA_VOL[6:0]
ADCMIXB_VOL[6:0]
MUTE_ADCMIXA
MUTE_ADCMIXB
SIGNAL PROCESSING ENGINE (SPE)
ADCA[1:0]
ADCB[1:0]
INPUTS FROM ADCA
and ADCB
Digital Mix to ADC
Serial Interface
Figure 12. Signal Processing Engine



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