CS53L21 datasheet(14/66 Pages) CIRRUS

14 / 66 page

DS700PP1

CS53L21

ADC DIGITAL FILTER CHARACTERISTICS

6. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 23 to 26) have

been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. HPF parameters

are for Fs = 48 kHz.

SWITCHING SPECIFICATIONS - SERIAL PORT

(Inputs: Logic 0 = DGND, Logic 1 = VL, SDOUT CLOAD = 15 pF.)

Parameter (Note 6)

Min

Typ

Max

Unit

Passband (Frequency Response)

to -0.1 dB corner

0.4948

Passband Ripple

-0.09

0.17

Stopband

0.6

Stopband Attenuation

Total Group Delay

7.6/Fs

High-Pass Filter Characteristics (48 kHz Fs)

Frequency Response

-3.0 dB

-0.13 dB

3.7

24.2

Phase Deviation

@ 20 Hz

-10-

Deg

Passband Ripple

0.17

Filter Settling Time

-105/Fs

Parameters

Symbol

Min

Max

Units

RESET pin Low Pulse Width

(Note 7)

MCLK Frequency

1.024

38.4

MHz

MCLK Duty Cycle

(Note 8)

Slave Mode

Input Sample Rate (LRCK)

Quarter-Speed Mode

Half-Speed Mode

Single-Speed Mode

Double-Speed Mode

12.5

100

kHz

LRCK Duty Cycle

SCLK Frequency

1/tP

-64•Fs

SCLK Duty Cycle

LRCK Setup Time Before SCLK Rising Edge

ts(LK-SK)

LRCK Edge to SDOUT MSB Output Delay

td(MSB)

-52

SDOUT Setup Time Before SCLK Rising Edge

ts(SDO-SK)

SDOUT Hold Time After SCLK Rising Edge

th(SK-SDO)

CS53L21 数据表(PDF) 14 Page - Cirrus Logic

CS53L21 数据表(HTML) 14 Page - Cirrus Logic

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