STV-6410-R01 datasheet(70/105 Pages) STMICROELECTRONICS

70 / 105 page

VV5410 & VV6410

Serial Control Bus

cd5410-6410f-3-0.fm

Commercial in confidence

70/105

[22],

[16] - data_format

Enable RESETB pin as SIN

Off / On

On power up the RESETB pin is conﬁgured as an

active low system reset which will synchronise the

video timing logic and reset all serial registers to

their default state. Setting this bit conﬁgures the

RESETB

active

high

system

synchronisation

signal

(SIN)

which

will

synchronise the video timing but will NOT reset the

serial registers.

7:6

unused

Mapping Enable

FST pin

QCK pin

FST

QCK

pin_mapping[2]

pin_mapping[1]

Table 38 : FST/QCK Pin Selection

oeb_composite

pin_map[4]

pin_map[3]

Comments

Drive strength = 2mA (Default)

Drive strength = 4mA

Drive strength = 6mA

unallocated

Outputs are not being driven therefore

driver strength is irrelevant

Table 39 : Output driver strength selection

Bit

Function

Default

Comment

1:0

Unused

Line read-out order (vertical)

Unshuffled or Shuffled

If the line read out is shuffled then all the even address

rows will be read out first followed by all the odd

address rows

Pixel read-out order (hmirror)

Normal or Mirrored

If the pixel read out is horizontally mirrored then the

columns are read out in reverse order, that is the

column on the right of the sensor array will appear on

the left of the displayed image and vice versa

Line read-out order (vertical flip)

Normal or Mirrored

If the line read out is vertically mirrored then the rows

are read out in reverse order, that is the row at the

bottom of the array will appear at the top of the

displayed image and vice versa.

Table 40 : [22],

[16] - data_format

Bit

Function

Default

Comment

Table 37 : [21],

[15] - pin_mapping

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