CC2500-RTR1 datasheet(39/84 Pages) TI

39 / 84 page

CC2500

PRELIMINARY Data Sheet (Rev.1.2)

SWRS040A

Page 39 of 83

The programmable conditions are:

•

MCSM2.RX_TIME_QUAL=0

Continue

receive if sync word has been found

•

MCSM2.RX_TIME_QUAL=1

Continue

receive if sync word has been found or

preamble quality is above threshold (PQT)

If the system can expect the transmission to

have started when enabling the receiver, the

MCSM2.RX_TIME_RSSI

function can be used.

The radio controller will then terminate RX if

the first valid carrier sense sample indicates

no carrier (RSSI below threshold). See Section

17.4 on page 32 for details on Carrier Sense.

For OOK modulation, lack of carrier sense is

only considered valid after eight symbol

periods. Thus, the MCSM2.RX_TIME_RSSI

function can be used in OOK mode when the

distance between “1” symbols is 8 or less.

If RX terminates due to no carrier sense when

the MCSM2.RX_TIME_RSSI function is used,

or if no sync word was found when using the

MCSM2.RX_TIME

timeout function, the chip

will always go back to IDLE if WOR is disabled

and back to SLEEP if WOR is enabled.

Otherwise, the MCSM1.RXOFF_MODE setting

determines the state to go to when RX ends.

Note that in wake-on-radio (WOR) mode, the

WOR state is cleared in the latter case. This

means that the chip will not automatically go

back to SLEEP again but to IDLE, even if e.g.

the address field in the packet did not match. It

is therefore recommended to always wake up

the microcontroller on sync word detection

when using WOR mode. This can be done by

selecting output signal 6 (see Table 33 on

page 47) on one of the programmable GDO

output

pins,

and

programming

the

microcontroller to wake up on an edge-

triggered interrupt from this GDO pin.

20 Data FIFO

The

CC2500 contains two 64 byte FIFOs, one

for received data and one for data to be

transmitted. The SPI interface is used to read

from the RX FIFO and write to the TX FIFO.

Section 10.5 contains details on the SPI FIFO

access. The FIFO controller will detect

overflow in the RX FIFO and underflow in the

TX FIFO.

When writing to the TX FIFO it is the

responsibility of the MCU to avoid TX FIFO

overflow. A TX FIFO overflow will result in an

error in the TX FIFO content.

Likewise, when reading the RX FIFO the MCU

must avoid reading the RX FIFO past its

empty value, since an RX FIFO underflow will

result in an error in the data read out of the RX

FIFO.

The chip status byte that is available on the SO

pin while transferring the SPI address contains

the fill grade of the RX FIFO if the address is a

read operation and the fill grade of the TX

FIFO if the address is a write operation.

Section 10.1on page 21 contains more details

on this.

The number of bytes in the RX FIFO and TX

FIFO can also be read from the status

registers

RXBYTES.NUM_RXBYTES

and

TXBYTES.NUM_TXBYTES

respectively. If a

received data byte is written to the RX FIFO at

the exact same time as the last byte in the RX

FIFO is read over the SPI interface, the RX

FIFO pointer is not properly updated and the

last read byte is duplicated.

For packet lengths less than 64 bytes it is

recommended to wait until the complete

packet has been received before reading it out

of the RX FIFO.

If the packet length is larger than 64 bytes the

MCU must determine how many bytes can be

read

from

the

FIFO

(RXBYTES.NUM_RXBYTES-1)

and

the

following software routine can be used:

1. Read

RXBYTES.NUM_RXBYTES

repeatedly at a rate guaranteed to be at

least twice that of which RF bytes are

received until the same value is returned

twice; store value in n

2. If n < # of bytes remaining in packet, read

-1 bytes from the RX FIFO.

3. Repeat steps 1 and 2 until n = # of bytes

remaining in the packet.

4. Read the remaining bytes from the RX

FIFO.

CC2500-RTR1 数据表(PDF) 39 Page - Texas Instruments

CC2500-RTR1 数据表(HTML) 39 Page - Texas Instruments

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