CC2500-RTR1 datasheet(41/84 Pages) TI

41 / 84 page

CC2500

PRELIMINARY Data Sheet (Rev.1.2)

SWRS040A

Page 41 of 83

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256

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⋅

CHANSPC

XOSC

carrier

CHANSPC

CHAN

FREQ

With a 26 MHz crystal the maximum channel

spacing is 405 kHz. To get e.g. 1 MHz channel

spacing one solution is to use 333 kHz

channel spacing and select each third channel

in CHANNR.CHAN.

The preferred IF frequency is programmed

with the FSCTRL1.FREQ_IF register. The IF

frequency is given by:

FREQ

XOSC

⋅

Note that the SmartRF

Studio software

automatically

calculates

the

optimum

FSCTRL1.FREQ_IF

channel spacing and channel filter bandwidth.

If any frequency programming register is

altered when the frequency synthesizer is

running,

the

synthesizer

may

give

undesired response. Hence, the frequency

programming should only be updated when

the radio is in the IDLE state.

22 VCO

The VCO is completely integrated on-chip.

22.1

VCO and PLL Self-Calibration

The VCO characteristics will vary with

temperature and supply voltage changes, as

well as the desired operating frequency. In

order to ensure reliable operation,

CC2500

includes frequency synthesizer self-calibration

circuitry. This calibration should be done

regularly, and must be performed after turning

on power and before using a new frequency

(or channel). The number of XOSC cycles for

completing the PLL calibration is given in

Table 28 on page 38.

The calibration can be initiated automatically

manually.

The

synthesizer

can

automatically

calibrated

each

time

the

synthesizer is turned on, or each time the

synthesizer is turned off. This is configured

with the MCSM0.FS_AUTOCAL register setting.

In manual mode, the calibration is initiated

when the SCAL command strobe is activated

in the IDLE mode.

Note that the calibration values are maintained

in sleep mode, so the calibration is still valid

after waking up from sleep mode (unless

supply voltage or temperature has changed

significantly).

To check that the PLL is in lock the user can

program register IOCFGx.GDOx_CFG to 0x0A

and use the lock detector output available on

the GDOx pin as an interrupt for the MCU (x =

0,1 or 2). A positive transition on the GDOx pin

means that the PLL is in lock. As an alternative

the user can read register FSCAL1. The PLL is

in lock if the register content is different from

0x3F. Refer also to the

CC2500 Errata Note.

For more robust operation the source code

could include a check so that the PLL is re-

calibrated until PLL lock is achieved if the PLL

does not lock the first time.

23 Voltage Regulators

CC2500 contains several on-chip linear voltage

regulators, which generate the supply voltage

needed

low-voltage

modules.

These

voltage regulators are invisible to the user, and

can be viewed as integral parts of the various

modules. The user must however make sure

that the absolute maximum ratings and

required pin voltages in Table 1 and Table 13

are not exceeded. The voltage regulator for

the

digital

core

requires

one

external

decoupling capacitor.

Setting the CSn pin low turns on the voltage

regulator to the digital core and starts the

crystal oscillator. The SO pin on the SPI

interface must go low before using the serial

interface (setup time is given in Table 16).

CC2500-RTR1 数据表(PDF) 41 Page - Texas Instruments

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