CC2500-RTR1 datasheet(29/84 Pages) TI

29 / 84 page

CC2500

PRELIMINARY Data Sheet (Rev.1.2)

SWRS040A

Page 29 of 83

15.3

Packet Filtering in Receive Mode

CC2500 supports three different packet-filtering

criteria: address filtering, maximum length

filtering and CRC filtering.

15.3.1 Address Filtering

Setting PKTCTRL1.ADR_CHK to any other

value than zero enables the packet address

filter. The packet handler engine will compare

the destination address byte in the packet with

the programmed node address in the ADDR

PKTCTRL1.ADR_CHK=10

or both 0x00 and

0xFF

broadcast

addresses

when

PKTCTRL1.ADR_CHK=11

the

received

address matches a valid address, the packet is

received and written into the RX FIFO. If the

address match fails, the packet is discarded

and receive mode restarted (regardless of the

MCSM1.RXOFF_MODE

setting).

If the received address matches a valid

address when the packet length is set to

infinite and address filtering is enabled, 0xFF

will be written into the RX FIFO followed by the

address byte and then the payload data.

15.3.2 Maximum Length Filtering

In the variable packet length mode the

PKTLEN.PACKET_LENGTH

used to set the maximum allowed packet

length. If the received length byte has a larger

value than this, the packet is discarded and

receive mode restarted (regardless of the

MCSM1.RXOFF_MODE

setting).

15.3.3 CRC Filtering

The filtering of a packet when CRC check fails

is enabled with PKTCTRL1.CRC_AUTOFLUSH.

The CRC auto flush function will flush the

entire

RX FIFO if the CRC check fails. After

auto flushing the RX FIFO, the next state

depends on the MCSM1.RXOFF_MODE setting.

PKTCTRL0.CC2400_EN

must be 0 (default)

for the CRC auto flush function to work

correctly.

When using the auto flush function, the

maximum packet length is 63 bytes in variable

packet length mode and 64 bytes in fixed

packet length mode. Note that the maximum

allowed packet length is reduced by two bytes

when

PKTCTRL1.APPEND_STATUS

enabled, to make room in the RX FIFO for the

two status bytes appended at the end of the

packet. Since the entire RX FIFO is flushed

when the CRC check fails, the previously

received packet must be read out of the FIFO

before receiving the current packet. The MCU

must not read from the current packet until the

CRC has been checked as OK.

15.4

CRC Check

There are two different CRC implementations.

PKTCTRL0.CC2400_EN

selects between the

2 options. The CRC check is different for the 2

options. Refer also to the

CC2500 Errata Note.

15.4.1 PKTCTRL0.CC2400_EN = 0

If PKTCTRL0.CC2400_EN =0 it is possible to

read back the CRC status in 2 different ways:

1) Set PKTCTRL1.APPEND_STATUS=1 and

read the CRC_OK flag in the MSB of the

second byte appended to the RX FIFO after

the packet data. This requires double buffering

of the packet, i.e. the entire packet content of

the RX FIFO must be completely read out

before it is possible to check whether the CRC

indication is OK or not.

2) To avoid reading the entire RX FIFO,

another

solution

use

the

PKTCTRL1.CRC_AUTOFLUSH

feature. If this

feature is enabled, the entire RX FIFO will be

flushed

the

CRC

check

fails.

GDOx_CFG

=0x06 the GDOx pin will be

asserted when a sync word is found. The

GDOx pin will be de-asserted at the end of the

packet. When the latter occurs the MCU

should read the number of bytes in the RX

FIFO

from

the

RXBYTES.NUM_RXBYTES

status register. If RXBYTES.NUM_RXBYTES=0

the CRC check failed and the FIFO is flushed.

If RXBYTES.NUM_RXBYTES>0 the CRC check

was OK and data can be read out of the FIFO.

15.4.2 PKTCTRL0.CC2400_EN = 1

If PKTCTRL0.CC2400_EN = 1 the CRC can be

checked as outlined in 1) in Section 15.4.1 as

well as by reading the CRC_OK flag available

in the PKTSTATUS[7] register, in the LQI[7]

status register or from one of the GDO pins if

GDOx_CFG

is 0x07 or 0x15.

The PKTCTRL1.CRC_AUTOFLUSH

or data

whitening

cannot

used

when

PKTCTRL0.CC2400_EN

= 1.

15.5

Packet Handling in Transmit Mode

The payload that is to be transmitted must be

written into the TX FIFO. The first byte written

must be the length byte when variable packet

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