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CC2500-RTR1 数据表(PDF) 24 Page - Texas Instruments |
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CC2500-RTR1 数据表(HTML) 24 Page - Texas Instruments |
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24 / 84 page ![]() CC2500 PRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 24 of 83 internally according to the control coding. It is only possible to change state with this functionality. That means that for instance RX will not be restarted if SI and SCLK are set to RX and CSn toggles. When CSn is low the SI and SCLK has normal SPI functionality. All pin control command strobes are executed immediately, except the SPWD strobe, which is delayed until CSn goes high. CSn SCLK SI Function 1 X X Chip unaffected by SCLK /SI ↓ 0 0 Generates SPWD strobe ↓ 0 1 Generates STX strobe ↓ 1 0 Generates SIDLE strobe ↓ 1 1 Generates SRX strobe 0 SPI mode SPI mode SPI mode (wakes up into IDLE if in SLEEP/XOFF) Table 18: Optional pin control coding 12 Data Rate Programming The data rate used when transmitting, or the data rate expected in receive is programmed by the MDMCFG3.DRATE_M and the MDMCFG4.DRATE_E configuration registers. The data rate is given by the formula below. As the formula shows, the programmed data rate depends on the crystal frequency. () XOSC E DRATE DATA f M DRATE R ⋅ ⋅ + = 28 _ 2 2 _ 256 The following approach can be used to find suitable values for a given data rate: 256 2 2 _ 2 log _ _ 28 20 2 − ⋅ ⋅ = ⎥ ⎥ ⎦ ⎥ ⎢ ⎢ ⎣ ⎢ ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ ⋅ = E DRATE XOSC DATA XOSC DATA f R M DRATE f R E DRATE If DRATE_M is rounded to the nearest integer and becomes 256, increment DRATE_E and use DRATE_M=0. The data rate can be set from 1.2 kbps to 500 kbps with the minimum step size of: Data rate start [kbps] Typical data rate [kbps] Data rate stop [kbps] Data rate step size [kbps] 0.8 1.2/2.4 3.17 0.0062 3.17 4.8 6.35 0.0124 6.35 9.6 12.7 0.0248 12.7 19.6 25.4 0.0496 25.4 38.4 50.8 0.0992 50.8 76.8 101.6 0.1984 101.6 153.6 203.1 0.3967 203.1 250 406.3 0.7935 406.3 500 500 1.5869 Table 19: Data rate step size 13 Receiver Channel Filter Bandwidth In order to meet different channel width requirements, the receiver channel filter is programmable. The MDMCFG4.CHANBW_E and MDMCFG4.CHANBW_M configuration registers control the receiver channel filter bandwidth, which scales with the crystal oscillator frequency. The following formula gives the relation between the register settings and the channel filter bandwidth: E CHANBW XOSC channel M CHANBW f BW _ 2 )· _ 4 ( 8 + ⋅ = The CC2500 supports the following channel filter bandwidths: |
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