CC2500-RTR1 datasheet(72/84 Pages) TI

72 / 84 page

CC2500

PRELIMINARY Data Sheet (Rev.1.2)

SWRS040A

Page 72 of 83

0x1F: WOREVT0 – Low byte Event0 timeout

Bit

Field Name

Reset

R/W

Description

7:0

EVENT0[7:0]

107 (0x6B)

R/W

Low byte of Event 0 timeout register.

The default Event 0 value gives 1.0 s timeout, assuming a

26.0 MHz crystal.

0x20: WORCTRL – Wake On Radio control

Bit

Field Name

Reset

R/W

Description

RC_PD

R/W

Power down signal to RC oscillator. When written to 0, automatic

initial calibration will be performed

6:4

EVENT1[2:0]

7 (111)

R/W

Timeout setting from register block. Decoded to Event 1 timeout.

RC oscillator clock frequency equals FXOSC/750, which is 34.7-36

kHz, depending on crystal frequency. The table below lists the

number of clock periods after Event 0 before Event 1 times out.

Setting

WOR_AUTOSYNC=0

WOR_AUTOSYNC=1

0 (000)

4 (0.111 – 0.115 ms)

1 (001)

6 (0.167 – 0.173 ms)

2 (010)

8 (0.222 – 0.230 ms)

3 (011)

12 (0.333 – 0.346 ms)

4 (100)

16 (0.444 – 0.462 ms)

5 (101)

24 (0.667 – 0.692 ms)

6 (110)

32 (0.889 – 0.923 ms)

7 (111)

48 (1.333 – 1.385 ms)

RC_CAL

R/W

Enables (1) or disables (0) the RC oscillator calibration.

Included for debug/test purposes only.

Reserved

1:0

WOR_RES[1:0]

0 (00)

R/W

Controls the Event 0 resolution and maximum timeout of the WOR

module:

Setting

Resolution (1 LSB)

Max timeout

0 (00)

1 period (28 – 29 µs)

1.8 – 1.9 seconds

1 (01)

5 periods (0.89 – 0.92 ms)

58 – 61 seconds

2 (10)

Do not use

3 (11)

Do not use

0x21: FREND1 – Front end RX configuration

Bit

Field Name

Reset

R/W

Description

7:6

LNA_CURRENT[1:0]

1 (01)

R/W

Adjusts front-end LNA PTAT current output

5:4

LNA2MIX_CURRENT[1:0]

1 (01)

R/W

Adjusts front-end PTAT outputs

3:2

LODIV_BUF_CURRENT_RX[1:0]

1 (01)

R/W

Adjusts current in RX LO buffer (LO input to mixer)

1:0

MIX_CURRENT[1:0]

2 (10)

R/W

Adjusts current in mixer

CC2500-RTR1 数据表(PDF) 72 Page - Texas Instruments

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