CC2500-RTR1 datasheet(22/84 Pages) TI

22 / 84 page

CC2500

PRELIMINARY Data Sheet (Rev.1.2)

SWRS040A

Page 22 of 83

burst bit in the address header. The address

sets the start address in an internal address

counter. This counter is incremented by one

each new byte (every 8 clock pulses). The

burst access is either a read or a write access

and must be terminated by setting CSn high.

For register addresses in the range 0x30-

0x3D, the “burst” bit is used to select between

status registers and command strobes (see

below). The status registers can only be read.

Burst read is not available for status registers,

so they must be read one at a time.

10.3

SPI Read

When reading register fields over the SPI

interface while the register fields are updated

by the radio hardware (e.g. MARCSTATE or

TXBYTES), there is a small, but finite,

probability that a single read from the register

is being corrupt. As an example, the

probability of any single read from TXBYTES

being corrupt, assuming the maximum data

rate is used, is approximately 80 ppm. Refer to

the

CC2500 Errata Note for more details.

10.4

Command Strobes

Command strobes may be viewed as single

byte instructions to

CC2500. By addressing a

command strobe register, internal sequences

will be started. These commands are used to

disable the crystal oscillator, enable receive

mode, enable wake-on-radio etc. The 14

command strobes are listed in Table 34 on

page 51.

The command strobe registers are accessed

in the same way as for a register write

operation, but no data is transferred. That is,

only the R/W bit (set to 0), burst access (set to

0) and the six address bits (in the range 0x30

through 0x3D) are written.

When writing command strobes, the status

byte is sent on the SO pin.

A command strobe may be followed by any

other SPI access without pulling CSn high.

After issuing an SRES command strobe the

next command strobe can be issued when the

pin goes low as shown in Figure 9. The

command strobes are executed immediately,

with the exception of the SPWD and the SXOFF

strobes that are executed when CSn goes

high.

Figure 9: SRES command strobe

10.5

FIFO Access

The 64-byte TX FIFO and the 64-byte RX

FIFO are accessed through the 0x3F address.

When the read/write bit is zero, the TX FIFO is

accessed, and the RX FIFO is accessed when

the read/write bit is one.

The TX FIFO is write-only, while the RX FIFO

is read-only.

The burst bit is used to determine if FIFO

access is single byte or a burst access. The

single byte access method expects address

with burst bit set to zero and one data byte.

After the data byte a new address is expected;

hence, CSn can remain low. The burst access

method expects one address byte and then

consecutive data bytes until terminating the

access by setting CSn high.

The following header bytes access the FIFOs:

•

0x3F: Single byte access to TX FIFO

•

0x7F: Burst access to TX FIFO

•

0xBF: Single byte access to RX FIFO

•

0xFF: Burst access to RX FIFO

When writing to the TX FIFO, the status byte

(see Section 10.1) is output for each new data

byte on SO, as shown in Figure 7. This status

byte can be used to detect TX FIFO underflow

while writing data to the TX FIFO. Note that

the status byte contains the number of bytes

free before writing the byte in progress to the

TX FIFO. When the last byte that fits in the TX

FIFO is transmitted to the SI pin, the status

byte received concurrently on the SO pin will

indicate that one byte is free in the TX FIFO.

The transmit FIFO may be flushed by issuing a

SFTX

command strobe. Similarly, a SFRX

command strobe will flush the receive FIFO. A

SFTX

or SFRX command strobe can only be

issued in the IDLE, TXFIFO_UNDERLOW or

RXFIFO_OVERFLOW state. Both FIFOs are

flushed when going to the SLEEP state.

CC2500-RTR1 数据表(PDF) 22 Page - Texas Instruments

CC2500-RTR1 数据表(HTML) 22 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

数据表下载