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CC2500-RTR1 数据表(PDF) 40 Page - Texas Instruments |
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CC2500-RTR1 数据表(HTML) 40 Page - Texas Instruments |
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40 / 84 page ![]() CC2500 PRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 40 of 83 The 4-bit FIFOTHR.FIFO_THR setting is used to program threshold points in the FIFOs. Table 29 lists the 16 FIFO_THR settings and the corresponding thresholds for the RX and TX FIFOs. The threshold value is coded in opposite directions for the RX FIFO and TX FIFO. This gives equal margin to the overflow and underflow conditions when the threshold is reached. A flag will assert when the number of bytes in the FIFO is equal to or higher than the programmed threshold. The flag is used to generate the FIFO status signals that can be viewed on the GDO pins (see Section 28 on page 46). Figure 20 shows the number of bytes in both the RX FIFO and TX FIFO when the threshold flag toggles, in the case of FIFO_THR=13. Figure 19 shows the flag as the respective FIFO is filled above the threshold, and then drained below. 53 54 55 56 53 54 55 56 57 6 7 8 9 6 7 8 9 10 NUM_RXBYTES GDO NUM_TXBYTES GDO Figure 19: FIFO_THR=13 vs. number of bytes in FIFO (GDOx_CFG=0x00 in Rx and GDOx_CFG =0x02 in Tx) FIFO_THR Bytes in TX FIFO Bytes in RX FIFO 0 (0000) 61 4 1 (0001) 57 8 2 (0010) 53 12 3 (0011) 49 16 4 (0100) 45 20 5 (0101) 41 24 6 (0110) 37 28 7 (0111) 33 32 8 (1000) 29 36 9 (1001) 25 40 10 (1010) 21 44 11 (1011) 17 48 12 (1100) 13 52 13 (1101) 9 56 14 (1110) 5 60 15 (1111) 1 64 Table 29: FIFO_THR settings and the corresponding FIFO thresholds 56 bytes 8 bytes Overflow margin Underflow margin FIFO_THR=13 FIFO_THR=13 RXFIFO TXFIFO Figure 20: Example of FIFOs at threshold 21 Frequency Programming The frequency programming in CC2500 is designed to minimize the programming needed in a channel-oriented system. To set up a system with channel numbers, the desired channel spacing is programmed with the MDMCFG0.CHANSPC_M and MDMCFG1.CHANSPC_E registers. The channel spacing registers are mantissa and exponent respectively. The base or start frequency is set by the 24 bit frequency word located in the FREQ2, FREQ1 and FREQ0 registers. This word will typically be set to the centre of the lowest channel frequency that is to be used. The desired channel number is programmed with the 8-bit channel number register, CHANNR.CHAN , which is multiplied by the channel offset. The resultant carrier frequency is given by: |
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