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UJA1069 数据表(PDF) 49 Page - NXP Semiconductors |
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UJA1069 数据表(HTML) 49 Page - NXP Semiconductors |
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49 / 64 page  UJA1069_2 © NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 02 — 5 March 2007 49 of 64 NXP Semiconductors UJA1069 LIN fail-safe system basis chip (1) Types 5V0, 3V3 and 3V0. (2) Type 5V0 only. a. At Tj = −40 °C, +25 °C and +150 °C. (1) Types 5V0, 3V3 and 3V0. (2) Types 3V3 and 3V0. b. At Tj = −40 °C to +150 °C. Fig 18. V1 quiescent current as a function of output current IV1 (mA) 0 −250 −200 −100 −150 −50 001aaf246 4 6 2 8 10 IBAT14 − IV1 (mA) 0 Tj = +150 °C 5.5 V(2) VBAT14 = 8 V(1) Tj = −40 °C +25 °C −40 °C +25 °C +150 °C IV1 (mA) 0 −250 −200 −100 −150 −50 001aaf247 2 3 1 4 5 IBAT14 − IV1 (mA) 0 VBAT14 = 9 V to 27 V(1) 5.5 V(2) |
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