UJA1069 datasheet(8/64 Pages) PHILIPS

8 / 64 page

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

8 of 64

NXP Semiconductors

UJA1069

LIN fail-safe system basis chip

Fig 4.

Main state diagram

001aad670

flash entry enabled (111/001/111 mode sequence)

OR mode change to Sleep with pending wake-up

OR watchdog not properly served

OR interrupt ignored

> tRSTN(INT)

OR RSTN falling edge detected

OR V1 undervoltage detected

OR illegal Mode register code

wake-up detected with its wake-up interrupt disabled

OR mode change to Sleep with pending wake-up

OR watchdog time-out with watchdog timeout interrupt disabled

OR watchdog OFF and IV1 > IthH(V1) with reset option

OR interrupt ignored

> tRSTN(INT)

OR RSTN falling edge detected

OR V1 undervoltage detected

OR illegal Mode register code

Start-up mode

V1: ON

SYSINH: HIGH

LIN: off-line

watchdog: start-up

INH/LIMP: HIGH/LOW/float

EN: LOW

Restart mode

V1: ON

SYSINH: HIGH

LIN: off-line

watchdog: start-up

INH/LIMP: LOW/float

EN: LOW

Sleep mode

V1: OFF

SYSINH: HIGH/float

LIN: off-line

watchdog: time-out/OFF

INH/LIMP: LOW/float

RSTN: LOW

EN: LOW

Fail-safe mode

V1: OFF

SYSINH: HIGH/float

LIN: off-line

watchdog: OFF

INH/LIMP: LOW

RSTN: LOW

EN: LOW

Normal mode

V1: ON

SYSINH: HIGH

LIN: all modes available

watchdog: window

INH/LIMP: HIGH/LOW/float

EN: HIGH/LOW

Flash mode

V1: ON

SYSINH: HIGH

LIN: all modes available

watchdog: time-out

INH/LIMP: HIGH/LOW/float

EN: HIGH/LOW

Standby mode

V1: ON

SYSINH: HIGH

LIN: off-line

watchdog: time-out/OFF

INH/LIMP: HIGH/LOW/float

EN: HIGH/LOW

mode change via SPI

wake-up detected

OR watchdog time-out

OR V3 overload detected

wake-up detected

AND oscillator ok

AND t

> tret

> tWD(init)

OR SPI clock count

<> 16

OR RSTN falling edge detected

OR RSTN released and V1 undervoltage detected

OR illegal Mode register code

> tWD(init)

OR SPI clock count

<> 16

OR RSTN falling edge detected

OR RSTN released and V1 undervoltage detected

OR illegal Mode register code

leave Flash mode code

OR watchdog time-out

OR interrupt ignored

> tRSTN(INT)

OR RSTN falling edge detected

OR V1 undervoltage detected

OR illegal Mode register code

init Flash mode via SPI

AND flash entry enabled

init Normal mode

via SPI successful

init Normal mode

via SPI successful

supply connected

for the first time

from any

mode

oscillator fail

OR RSTN externally clamped HIGH detected

> tRSTN(CHT)

OR RSTN externally clamped LOW detected

> tRSTN(CLT)

OR V1 undervoltage detected

> tV1(CLT)

watchdog

trigger

watchdog

trigger

mode change via SPI

watchdog

trigger

UJA1069 数据表(PDF) 8 Page - NXP Semiconductors

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UJA1069 数据表(PDF) 8 Page - NXP Semiconductors

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