UJA1069 datasheet(22/64 Pages) PHILIPS

22 / 64 page

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

22 of 64

NXP Semiconductors

UJA1069

LIN fail-safe system basis chip

When pin INH/LIMP is used as inhibit output, a pull-down resistor to GND ensures a

default LOW level. The pin can be set to HIGH according to the state diagram.

When pin INH/LIMP is used as limp-home output, a pull-up resistor to VBAT42 ensures a

default HIGH level. The pin is automatically set to LOW when the SBC enters Fail-safe

mode.

6.9 Wake-up input

The WAKE input comparator is triggered by negative edges on pin WAKE. Pin WAKE has

an internal pull-up resistor to BAT42. It can be operated in two sampling modes which are

selected via the WAKE Sample Control bit (WSC):

• Continuous sampling (with an internal clock) if the bit is set

• Sampling synchronized to the cyclic behavior of V3 if the bit is cleared; see Figure 13.

This is to save bias current within the external switches in low-power operation. Two

repetition times are possible, 16 ms and 32 ms.

If V3 is continuously ON, the WAKE input will be sampled continuously, regardless of the

level of bit WSC.

The dedicated bits Edge Wake-up Status (EWS) and WAKE Level Status (WLS) in the

System Status register reﬂect the actual status of pin WAKE. The WAKE port can be

disabled by clearing the WEN bit in the System Conﬁguration register.

Fig 12. States of the INH/LIMP pin

001aad178

INH/LIMP:

HIGH

ILEN = 1

ILC = 1

INH/LIMP:

floating

ILEN = 0

ILC = 1/0

ILEN = 1

ILC = 0

INH/LIMP:

LOW

state change via SPI

OR enter Fail-safe mode

state change via SPI

OR (enter Start-up mode after

wake-up reset, external reset

or V1 undervoltage)

OR enter Restart mode

OR enter Sleep mode

state change via SPI

power-on

state change via SPI

OR enter Fail-safe mode

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