UJA1069 datasheet(24/64 Pages) PHILIPS

24 / 64 page

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

24 of 64

NXP Semiconductors

UJA1069

LIN fail-safe system basis chip

6.12 SPI interface

The Serial Peripheral Interface (SPI) provides the communication link with the

microcontroller, supporting multi-slave and multi-master operation. The SPI is conﬁgured

for full duplex data transfer, so status information is returned when new control data is

shifted in. The interface also offers a read-only access option, allowing registers to be

read back by the application without changing the register content.

The SPI uses four interface signals for synchronization and data transfer:

• SCS - SPI chip select; active LOW

• SCK - SPI clock; default level is LOW due to low-power concept

• SDI - SPI data input

• SDO - SPI data output; ﬂoating when pin SCS is HIGH

Bit sampling is performed on the falling clock edge and data is shifted on the rising clock

edge; see Figure 14.

To protect against wrong or illegal SPI instructions, the SBC detects the following SPI

failures:

• SPI clock count failure (wrong number of clock cycles during one SPI access): only

16 clock periods are allowed within one SCS cycle. Any deviation from the 16 clock

cycles results in an SPI failure interrupt, if enabled. The access is ignored by the SBC.

In Start-up and Restart mode a reset is forced instead of an interrupt

• Forbidden mode changes according to Figure 4 result in an immediate system reset

• Illegal Mode register code. Undeﬁned operating mode or watchdog period coding

results in an immediate system reset; see Section 6.12.3

Fig 14. SPI timing protocol

SCS

SCK

sampled

floating

mce634

MSB

LSB

MSB

LSB

SDI

SDO

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