UJA1069 datasheet(29/64 Pages) PHILIPS

29 / 64 page

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

29 of 64

NXP Semiconductors

UJA1069

LIN fail-safe system basis chip

[1]

The RSS bits are updated with each reset event and not cleared. The last reset event is captured.

6.12.5 System Diagnosis register

This register allows diagnosis information to be read back from the SBC. This register can

be read in all modes.

11 to 8

RSS[3:0]

Reset Source[1]

0000

power-on reset; ﬁrst connection of BAT42 or BAT42 below

power-on voltage threshold or RSTN was forced LOW

externally

0001

cyclic wake-up out of Sleep mode

0010

low V1 supply; V1 has dropped below the selected reset

threshold

0011

V1 current above threshold within Standby mode while

watchdog OFF behavior and reset option (V1CMC bit) are

selected

0100

V3 voltage is down due to overload occurring during Sleep

mode

0101

SBC successfully left Flash mode

0110

SBC ready to enter Flash mode

0111

reserved for SBCs with CAN transceiver

1000

LIN wake-up event

1001

local wake-up event (via pin WAKE)

1010

wake-up out of Fail-safe mode

1011

watchdog overﬂow

1100

watchdog not initialized in time; tWD(init) exceeded

1101

watchdog triggered too early; window missed

1110

illegal SPI access

1111

interrupt not served within tRSTN(INT)

reserved

reserved for SBCs with CAN transceiver

LWS

LIN Wake-up Status

LIN wake-up detected; cleared upon read

no LIN wake-up

EWS

Edge Wake-up Status

pin WAKE negative edge detected; cleared upon read

pin WAKE no edge detected

WLS

WAKE Level Status

pin WAKE above threshold

pin WAKE below threshold

TWS

Temperature Warning

Status

chip temperature exceeds the warning limit

chip temperature is below the warning limit

SDMS

Software Development

Mode Status

Software Development mode on

Software Development mode off

ENS

Enable Status

pin EN output activated (V1-related HIGH level)

pin EN output released (LOW level)

PWONS

Power-on reset Status

power-on reset; cleared after a successfully entered

Normal mode

no power-on reset

Table 6.

System Status register bit description …continued

Bit

Symbol

Description

Value

Function

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