UJA1069 datasheet(25/64 Pages) PHILIPS

25 / 64 page

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

25 of 64

NXP Semiconductors

UJA1069

LIN fail-safe system basis chip

6.12.1 SPI register mapping

Any control bit which can be set by software is readable by the application. This allows

software debugging as well as control algorithms to be implemented.

Watchdog serving and mode setting is performed within the same access cycle; this only

allows an SBC mode change whilst serving the watchdog.

Each register carries 12 data bits; the other 4 bits are used for register selection and

read/write deﬁnition.

6.12.2 Register overview

The SPI interface gives access to all SBC registers; see Table 3. The ﬁrst two bits (A1 and

A0) of the message header deﬁne the register address, the third bit is the read register

select bit (RRS) to select one out of two possible feedback registers; the fourth bit (RO)

allows ‘read only’ access to one of the feedback registers. Which of the SBC registers can

be accessed also depends on the SBC operating mode.

6.12.3 Mode register

In the Mode register the watchdog is deﬁned and re-triggered, and the SBC operating

mode is selected. The Mode register also contains the global enable output bit (EN) and

the Software Development Mode (SDM) control bit. During system operation cyclic access

to the Mode register is required to serve the watchdog. This register can be written to in all

modes.

At system start-up the Mode register must be written to within tWD(init) from releasing

RSTN (HIGH-level on pin RSTN). Any write access is checked for proper watchdog and

system mode coding. If an illegal code is detected, access is ignored by the SBC and a

system reset is forced in accordance with the state diagram of the system controller; see

Figure 4.

Table 3.

address bits

(A1, A0)

Operating

mode

Write access (RO = 0)

Read access (RO = 0 or RO = 1)

Read Register Select

(RRS) bit = 0

Read Register Select

(RRS) bit = 1

all modes

Mode register

System Status register

System Diagnosis register

Normal mode;

Standby mode;

Flash mode

Interrupt Enable register

Interrupt Enable Feedback

Interrupt register

Start-up mode;

Restart mode

Special Mode register

Interrupt Enable Feedback

Special Mode Feedback

Normal mode;

Standby mode

System Conﬁguration

Feedback register

General Purpose Feedback

Start-up mode;

Restart mode;

Flash mode

General Purpose register 0

System Conﬁguration

Feedback register

General Purpose Feedback

Normal mode;

Standby mode

Physical Layer Control

Feedback register

General Purpose Feedback

Start-up mode;

Restart mode;

Flash mode

General Purpose register 1

Physical Layer Control

Feedback register

General Purpose Feedback

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