ST92F124 datasheet(58/429 Pages) STMICROELECTRONICS

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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM)

Bit 2 = WFIS: Wait For Interrupt Status.

If this bit is reset, the WFI instruction puts the

Flash macrocell in Stand-by mode (immediate

read possible, but higher consumption: 100

µA); if

it is set, the WFI instruction puts the Flash macro-

cell in Power-Down mode (recovery time of 10

µs

needed before reading, but lower consumption:

µA). The Stand-by mode or the Power-Down

mode will be entered only at the end of any current

Flash or E3 TM write operation.

In the same way following an HALT or a STOP in-

struction, the Memory enters Power-Down mode

only after the completion of any current write oper-

ation.

0: Flash in Stand-by mode on WFI

1: Flash in Power-Down mode on WFI

Note: HALT or STOP mode can be exited without

problems, but the user should take care when ex-

iting WFI Power Down mode. If WFIS is set, the

user code must reset the XT_DIV16 bit in the

R242 register (page 55) before executing the WFI

instruction. When exiting WFI mode, this gives the

Flash enough time to wake up before the interrupt

vector fetch.

Bit 1 = FEIEN: Flash & E3 TM Interrupt enable.

This bit selects the source of interrupt channel

INTx between the external interrupt pin and the

Flash/E3 TM End of Write interrupt. Refer to the In-

terrupt chapter for the channel number.

0: External interrupt enabled

1: Flash & E3 TM Interrupt enabled

Bit 0 = EBUSY: E3 TM Busy (Read Only).

This bit is automatically set during a Page Update

operation when the first address to be modified is

latched in the E3 TM memory, or during Chip Erase

operation when bit EWMS is set. At the end of the

write operation or during a Sector Erase Suspend

this bit is automatically reset and the memory re-

turns to read mode. When this bit is set every read

access to the E3 TM memory will output invalid data

(FFh equivalent to a NOP instruction), while every

write access to the E3 TM memory will be ignored.

At the end of the write operation this bit is automat-

ically reset and the memory returns to read mode.

Bit EBUSY remains high for a maximum of 10ms

after Power-Up and when exiting Power-Down

mode, meaning that the E3 TM memory is not yet

ready to be accessed.

0: E3 TM not busy

1: E3 TM busy

3.3.2 Status Registers

Two Status Registers (FESR[1:0] are available to

check the status of the current write operation in

Flash and E3 TM memories.

During a Flash or an E3 TM write operation any at-

tempt to read the memory under modification will

output invalid data (FFh equivalent to a NOP in-

struction). This means that the Flash memory is

not fetchable when a write operation is active: the

write operation commands must be given from an-

other memory (E3 TM, internal RAM, or external

memory).

FLASH & E3 TM STATUS REGISTER 0 (FESR0)

Address: 224002h /221002h -Read/Write

Reset value: 0000 0000 (00h)

Bit 7 = FEERR: Flash or E3 TM write ERRor (Read/

Write).

This bit is set by hardware when an error occurs

during a Flash or an E3 TM write operation. It must

be cleared by software.

0: Write OK

1: Flash or E3 TM write error

Bit 6:0 = FESS[6:0]. Flash and E3 TM Sectors Sta-

tus Bits (Read Only).

These bits are set by hardware and give the status

of the 7 Flash and E3 TM sectors.

– FESS6 = TestFlash and OTP

– FESS5:4 = E3 TM sectors

For 128K and 64K Flash devices:

– FESS3:0 = Flash sectors (F3:0)

For the ST92F250 (256K):

– FESS3 gives the status of F5, F4 and F3 sectors:

the status of all these three sectors are ORed on

this bit

– FESS2:0 = Flash sectors (F2:0)

321

FEERR FESS6 FESS5 FESS4 FESS3 FESS2 FESS1 FESS0

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