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ST92F124/F150/F250 - INTERRUPTS

The Top Level Interrupt vector is located at ad-

dresses 0004h and 0005h in the segment pointed

to by the Interrupt Segment Register (ISR).

If an external watchdog is used, refer to the Regis-

ter and Memory Map section for details on using

vector locations 0006h to 0009h. Otherwise loc-

tions 0006h to 0007h must contain FFFFh.

With one Interrupt Vector register, it is possible to

address several interrupt service routines; in fact,

peripherals can share the same interrupt vector

most significant bits of the vector are user pro-

grammable to define the base vector address with-

in the vector table, the least significant bits are

controlled by the interrupt module, in hardware, to

select the appropriate vector.

Note: The first 256 locations of the memory seg-

ment pointed to by ISR can contain program code.

5.2.1 Divide by Zero trap

The Divide by Zero trap vector is located at ad-

dresses 0002h and 0003h of each code segment;

it should be noted that for each code segment a

Divide by Zero service routine is required.

Warning. Although the Divide by Zero Trap oper-

ates as an interrupt, the FLAG Register is not

pushed onto the system Stack automatically. As a

result it must be regarded as a subroutine, and the

service routine must end with the RET instruction

(not IRET ).

5.2.2

Segment

Paging

During

Interrupt

Routines

The ENCSR bit in the EMR2 register can be used

to select between original ST9 backward compati-

bility mode and ST9+ interrupt management

mode.

ST9 backward compatibility mode (ENCSR = 0)

If ENCSR is reset, the CPU works in original ST9

compatibility mode. For the duration of the inter-

rupt service routine, ISR is used instead of CSR,

and the interrupt stack frame is identical to that of

the original ST9: only the PC and Flags are

pushed.

This avoids saving the CSR on the stack in the

event of an interrupt, thus ensuring a faster inter-

rupt response time.

It is not possible for an interrupt service routine to

perform inter-segment calls or jumps: these in-

structions would update the CSR, which, in this

case, is not used (ISR is used instead). The code

segment size for all interrupt service routines is

thus limited to 64K bytes.

ST9+ mode (ENCSR = 1)

If ENCSR is set, ISR is only used to point to the in-

terrupt vector table and to initialize the CSR at the

beginning of the interrupt service routine: the old

CSR is pushed onto the stack together with the PC

and flags, and CSR is then loaded with the con-

tents of ISR.

In this case, iret will also restore CSR from the

stack. This approach allows interrupt service rou-

tines to access the entire 4 Mbytes of address

space. The drawback is that the interrupt response

time is slightly increased, because of the need to

also save CSR on the stack.

Full compatibility with the original ST9 is lost in this

case, because the interrupt stack frame is differ-

ent.

ENCSR Bit

Mode

ST9 Compatible

ST9+

Pushed/Popped

Registers

PC, FLAGR

PC, FLAGR,

CSR

Max. Code Size

for interrupt

service routine

64KB

Within 1 segment

No limit

Across segments

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