ST92F124 datasheet(33/429 Pages) STMICROELECTRONICS

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ST92F124/F150/F250 - DEVICE ARCHITECTURE

MEMORY SPACES (Cont’d)

2.2.2 Register Addressing

registers (but excluding Group D), may be ad-

dressed explicitly by means of a decimal, hexa-

decimal or binary address; thus R231, RE7h and

R11100111b

represent the same register (see

Figure 21). Group D registers can only be ad-

dressed in Working Register mode.

Note that an upper case “R” is used to denote this

direct addressing mode.

Working Registers

Certain types of instruction require that registers

be specified in the form “rx”, where x is in the

range 0 to 15: these are known as Working Regis-

ters.

Note that a lower case “r” is used to denote this in-

direct addressing mode.

Two addressing schemes are available: a single

group of 16 working registers, or two separately

mapped groups, each consisting of 8 working reg-

isters. These groups may be mapped starting at

any 8 or 16 byte boundary in the register file by

means of dedicated pointer registers. This tech-

nique is described in more detail in Section 2.3.3

Figure 22 and in Figure 23.

System Registers

The 16 registers in Group E (R224 to R239) are

System registers and may be addressed using any

of the register addressing modes. These registers

are described in greater detail in Section 2.3 SYS-

TEM REGISTERS.

Paged Registers

Up to 64 pages, each containing 16 registers, may

be mapped to Group F. These are addressed us-

ing any register addressing mode, in conjunction

with the Page Pointer register, R234, which is one

of the System registers. This register selects the

page to be mapped to Group F and, once set,

does not need to be changed if two or more regis-

ters on the same page are to be addressed in suc-

cession.

Therefore if the Page Pointer, R234, is set to 5, the

instructions:

spp #5

ld R242, r4

will load the contents of working register r4 into the

third register of page 5 (R242).

These paged registers hold data and control infor-

mation relating to the on-chip peripherals, each

peripheral always being associated with the same

pages and registers to ensure code compatibility

between ST9 devices. The number of these regis-

ters therefore depends on the peripherals which

are present in the specific ST9 family device. In

other words, pages only exist if the relevant pe-

ripheral is present.

Table 5. Register File Organization

Hex.

Address

Decimal

Address

Function

File Group

F0-FF

240-255

Paged

Registers

Group F

E0-EF

224-239

System

Registers

Group E

D0-DF

208-223

General

Purpose

Registers

Group D

C0-CF

192-207

Group C

B0-BF

176-191

Group B

A0-AF

160-175

Group A

90-9F

144-159

Group 9

80-8F

128-143

Group 8

70-7F

112-127

Group 7

60-6F

96-111

Group 6

50-5F

80-95

Group 5

40-4F

64-79

Group 4

30-3F

48-63

Group 3

20-2F

32-47

Group 2

10-1F

16-31

Group 1

00-0F

00-15

Group 0

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