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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM)

3.6 FLASH IN-SYSTEM PROGRAMMING

The Flash memory can be programmed in-system

through a serial interface (SCI0).

Exiting from reset, the ST9 executes the initializa-

tion from the TestFlash code (written in Test-

Flash), where it checks the value of the SOUT0

pin. If it is at 0, this means that the user wishes to

update the Flash code, otherwise normal execu-

tion continues. In this second case, the TestFlash

code reads the Reset vector.

If the Flash is virgin (read content is always FFh),

the reset vector contains FFFFh. This will repre-

sent the last location of segment 0h, and it is inter-

preted by the TestFlash code as a flag indicating

that the Flash memory is virgin and needs to be

programmed. If the value 1 is detected on the

SOUT0 pin and the Flash is virgin, a HALT instruc-

tion is executed, waiting for a hardware Reset.

3.6.1 Code Update Routine

The TestFlash Code Update routine is called auto-

matically if the SOUT0 pin is held low during pow-

er-on.

The Code Update routine performs the following

operations:

■ Enables the SCI0 peripheral in synchronous

mode

■ Transmits a synchronization datum (25h);

■ Waits for an address match (23h) with a timeout

of 10ms (@ fOSC 4 MHz);

■ If the match is not received before the timeout,

the execution returns to the Power-On routine;

■ If the match is received, the SCI0 transmits a

new datum (21h) to tell the external device that

it is ready to receive the data to be loaded in

RAM (that represents the code of the in-system

programming routine);

■ Receives two data representing the number of

bytes to be loaded (max. 4 Kbytes);

■ Receives the specified number of bytes (each

one preceded by the transmission of a Ready to

Receive character: (21h) and writes them in

internal RAM starting from address 200010h.

The first 4 words should be the interrupt vectors

of the 4 possible SCI interrupts, to be used by

the in-system programming routine;

■ Transmits a last datum (21h) as a request for

end of communications;

■ Receives

the

end

communication

confirmation datum (any byte other than 25h);

■ Resets all the unused RAM locations to FFh;

■ Calls address 200018h in internal RAM;

■ After completion of the in-system programming

routine, an HALT instruction is executed and an

Hardware Reset is needed.

The Code Update routine initializes the SCI0 pe-

ripheral as shown in the following table:

Table 13. SCI0 Registers (page 24) initialization

In addition, the Code Update routine remaps the

interrupts in the TestFlash (ISR = 23h), and config-

ures I/O Ports P5.3 (SOUT0) and and P5.4

(CLKOUT0) as Alternate Functions.

Note: Four interrupt routines are used by the code

update routine: SCI Receiver Error Interrupt rou-

tine (vector in 0010h), SCI address Match Interrupt

routine (vector in 0012h), SCI Receiver Data

Ready Interrupt routine (vector in 0014h) and SCI

Transmitter Buffer Empty Interrupt routine (vector

in 0016h).

Value

Notes

IVR - R244

10h

Vector Table in 0010h

ACR - R245

23h

Address Match is 23h

IDPR - R249

00h

SCI interrupt priority is 0

CHCR - R250

83h

8 Data Bits

CCR - R251

E8h

rec. clock: ext RXCLK0

trx clock: int CLKOUT0

BRGHR - R252

00h

BRGLR - R253

04h

Baud Rate Divider is 4

SICR - R254

83h

Synchronous Mode

SOCR - R255

01h

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