ST92F124 datasheet(94/429 Pages) STMICROELECTRONICS

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ST92F124/F150/F250 - INTERRUPTS

5.3 INTERRUPT PRIORITY LEVELS

The ST9 supports a fully programmable interrupt

priority structure. Nine priority levels are available

to define the channel priority relationships:

– The on-chip peripheral channels and the eight

external interrupt sources can be programmed

within eight priority levels. Each channel has a 3-

bit field, PRL (Priority Level), that defines its pri-

ority level in the range from 0 (highest priority) to

7 (lowest priority).

– The 9th level (Top Level Priority) is reserved for

the Timer/Watchdog or the External Pseudo

Non-Maskable Interrupt. An Interrupt service

routine at this level cannot be interrupted in any

arbitration mode. Its mask can be both maskable

(TLI) or non-maskable (TLNM).

5.4 PRIORITY LEVEL ARBITRATION

The 3 bits of CPL (Current Priority Level) in the

Central Interrupt Control Register contain the pri-

ority of the currently running program (CPU priori-

ty). CPL is set to 7 (lowest priority) upon reset and

can be modified during program execution either

by software or automatically by hardware accord-

ing to the selected Arbitration Mode.

During every instruction, an arbitration phase

takes place, during which, for every channel capa-

ble of generating an Interrupt, each priority level is

compared to all the other requests (interrupts or

DMA).

If the highest priority request is an interrupt, its

PRL value must be strictly lower (that is, higher pri-

ority) than the CPL value stored in the CICR regis-

ter (R230) in order to be acknowledged. The Top

Level Interrupt overrides every other priority.

5.4.1 Priority Level 7 (Lowest)

Interrupt requests at PRL level 7 cannot be ac-

knowledged, as this PRL value (the lowest possi-

ble priority) cannot be strictly lower than the CPL

value. This can be of use in a fully polled interrupt

environment.

5.4.2 Maximum Depth of Nesting

No more than 8 routines can be nested. If an inter-

rupt routine at level N is being serviced, no other

Interrupts located at level N can interrupt it. This

guarantees a maximum number of 8 nested levels

including the Top Level Interrupt request.

5.4.3 Simultaneous Interrupts

If two or more requests occur at the same time and

at the same priority level, an on-chip daisy chain,

specific to every ST9 version, selects the channel

with the highest position in the chain, as shown in

Table 18

Table 18. Daisy Chain Priority

* available on some devices only

5.4.4 Dynamic Priority Level Modification

The main program and routines can be specifically

prioritized. Since the CPL is represented by 3 bits

in a read/write register, it is possible to dynamically

modify the current priority value during program

execution. This means that a critical section can

have a higher priority with respect to other inter-

rupt requests. Furthermore it is possible to priori-

tize even the Main Program execution by modify-

ing the CPL during its execution. See Figure 45.

Highest Position

Lowest Position

INTA0 / Watchdog Timer

INTA1 / Standard Timer

INTB0 / Extended Function Timer 0 *

INTB1 / Extended Function Timer 1 *

INTC0 / E3 TM/Flash

INTC1 / SPI

INTD0 / RCCU

INTD1 / WKUP MGT

Multifunction Timer 0

INTE0/CAN0_RX0

INTE1/CAN0_RX1

INTF0/CAN0_TX

INTF1/CAN0_SCE

INTG0/CAN1_RX0 *

INTG1/CAN1_RX1 *

INTH0/CAN1_TX *

INTH1/CAN1_SCE *

INTI0/SCI-A *

JBLPD *

I2C bus Interface 0

I2C bus Interface 1 *

A/D Converter

Multifunction Timer 1

SCI-M

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