ST92F124 datasheet(44/429 Pages) STMICROELECTRONICS

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ST92F124/F150/F250 - DEVICE ARCHITECTURE

2.6 ADDRESS SPACE EXTENSION

To manage 4 Mbytes of addressing space, it is

necessary to have 22 address bits. The MMU

adds 6 bits to the usual 16-bit address, thus trans-

lating a 16-bit virtual address into a 22-bit physical

address. There are 2 different ways to do this de-

pending on the memory involved and on the oper-

ation being performed.

2.6.1 Addressing 16-Kbyte Pages

This extension mode is implicitly used to address

Data memory space if no DMA is being performed.

The Data memory space is divided into 4 pages of

16 Kbytes. Each one of the four 8-bit registers

(DPR[3:0], Data Page Registers) selects a differ-

ent 16-Kbyte page. The DPR registers allow ac-

cess to the entire memory space which contains

256 pages of 16 Kbytes.

Data paging is performed by extending the 14 LSB

of the 16-bit address with the contents of a DPR

interpreted as the identification number of the DPR

are involved in the following virtual address rang-

es:

DPR0: from 0000h to 3FFFh;

DPR1: from 4000h to 7FFFh;

DPR2: from 8000h to BFFFh;

DPR3: from C000h to FFFFh.

The contents of the selected DPR register specify

one of the 256 possible data memory pages. This

8-bit data page number, in addition to the remain-

ing 14-bit page offset address forms the physical

22-bit address (see Figure 27).

A DPR register cannot be modified via an address-

ing mode that uses the same DPR register. For in-

stance, the instruction “POPW DPR0” is legal only

if the stack is kept either in the register file or in a

memory location above 8000h, where DPR2 and

DPR3 are used. Otherwise, since DPR0 and

DPR1 are modified by the instruction, unpredicta-

ble behaviour could result.

Figure 27. Addressing via DPR[3:0]

DPR0

DPR1

DPR2

DPR3

16-bit virtual address

22-bit physical address

8 bits

MMU registers

2 M

14 LSB

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