ST92F124 datasheet(11/429 Pages) STMICROELECTRONICS

11 / 429 page

11/429

ST92F124/F150/F250 - GENERAL DESCRIPTION

1.2 PIN DESCRIPTION

AS. Address Strobe (output, active low, 3-state).

Address Strobe is pulsed low once at the begin-

ning of each memory cycle. The rising edge of AS

indicates that address, Read/Write (RW), and

Data signals are valid for memory transfers.

DS. Data Strobe (output, active low, 3-state). Data

Strobe provides the timing for data movement to or

from Port 0 for each memory transfer. During a

write cycle, data out is valid at the leading edge of

DS. During a read cycle, Data In must be valid pri-

or to the trailing edge of DS. When the ST9 ac-

cesses on-chip memory, DS is held high during

the whole memory cycle.

RESET. Reset (input, active low). The ST9 is ini-

tialised by the Reset signal. With the deactivation

of RESET, program execution begins from the

Program memory location pointed to by the vector

contained in program memory locations 00h and

01h.

RW. Read/Write (output, 3-state). Read/Write de-

termines the direction of data transfer for external

memory transactions. RW is low when writing to

external memory, and high for all other transac-

tions.

OSCIN, OSCOUT. Oscillator (input and output).

These pins connect a parallel-resonant crystal, or

an external source to the on-chip clock oscillator

and buffer. OSCIN is the input of the oscillator in-

verter; OSCOUT is the output of the oscillator in-

verter.

HW0SW1. When connected to VDD through a 1K

pull-up resistor, the software watchdog option is

selected. When connected to VSS through a 1K

pull-down resistor, the hardware watchdog option

is selected.

VPWO. This pin is the output line of the J1850 pe-

ripheral (JBLPD). It is available only on some de-

vices.

RX1/WKUP6. Receive Data input of CAN1 and

Wake-up line 6. Available only on some devices.

When the CAN1 peripheral is disabled, a pull-up

resistor is connected internally to this pin.

TX1. Transmit Data output of CAN1. Available on

some devices.

P0[7:0], P1[7:0] or P9[7:2] (Input/Output, TTL or

CMOS compatible). 11 lines (64-pin devices) or 22

lines (100-pin devices) providing the external

memory interface for addressing 2K or 4M bytes of

external memory.

P0[7:0],

P1[2:0],

P2[7:0],

P3[7:4],

P4.[7:4],

P5[7:0], P6[5:2,0], P7[7:0] I/O Port Lines (Input/

Output, TTL or CMOS compatible). I/O lines

grouped into I/O ports of 8 bits, bit programmable

under software control as general purpose I/O or

as alternate functions.

P1[7:3], P3[3:1], P4[3:0], P6.1, P8[7:0], P9[7:0]

Additional I/O Port Lines available on 100-pin ver-

sions only.

P3.0, P6[7:6] Additional I/O Port Lines available

on ST92F250 version only.

AVDD. Analog VDD of the Analog to Digital Con-

verter (common for ADC 0 and ADC 1).

AVDD can be switched off when the ADC is not in

use.

AVSS. Analog VSS of the Analog to Digital Con-

verter (common for ADC 0 and ADC 1).

VDD. Main Power Supply Voltage. Four pins are

available on 100-pin versions, two on 64-pin ver-

sions. The pins are internally connected.

VSS. Digital Circuit Ground. Four pins are availa-

ble on 100-pin versions, two on 64-pin versions.

The pins are internally connected.

VTEST Power Supply Voltage for Flash test pur-

poses. This pin must be kept to 0 in user mode.

VREG. Stabilization capacitors for the internal volt-

age regulator. The user must connect external sta-

bilization capacitors to these pins. Refer to Figure

16.

1.2.1 I/O Port Alternate Functions

Each pin of the I/O ports of the ST92F124/F150/

F250 may assume software programmable Alter-

nate Functions as shown in Section 1.4.

1.2.2 Termination of Unused Pins

For unused pins, input mode is not recommended.

These pins must be kept at a fixed voltage using

the output push pull mode of the I/O or an external

pull-up or pull-down resistor.

ST92F124 数据表(PDF) 11 Page - STMicroelectronics

ST92F124 数据表(HTML) 11 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载