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ST92F124 数据表(PDF) 95 Page - STMicroelectronics |
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ST92F124 数据表(HTML) 95 Page - STMicroelectronics |
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95 / 429 page ![]() 95/429 ST92F124/F150/F250 - INTERRUPTS Figure 45. Example of Dynamic Priority Level Modification in Nested Mode 5.5 ARBITRATION MODES The ST9 provides two interrupt arbitration modes: Concurrent mode and Nested mode. Concurrent mode is the standard interrupt arbitration mode. Nested mode improves the effective interrupt re- sponse time when service routine nesting is re- quired, depending on the request priority levels. The IAM control bit in the CICR Register selects Concurrent Arbitration mode or Nested Arbitration Mode. 5.5.1 Concurrent Mode This mode is selected when the IAM bit is cleared (reset condition). The arbitration phase, performed during every instruction, selects the request with the highest priority level. The CPL value is not modified in this mode. Start of Interrupt Routine The interrupt cycle performs the following steps: – All maskable interrupt requests are disabled by clearing CICR.IEN. – The PC low byte is pushed onto system stack. – The PC high byte is pushed onto system stack. – If ENCSR is set, CSR is pushed onto system stack. – The Flag register is pushed onto system stack. – The PC is loaded with the 16-bit vector stored in the Vector Table, pointed to by the IVR. – If ENCSR is set, CSR is loaded with ISR con- tents; otherwise ISR is used in place of CSR until iret instruction. End of Interrupt Routine The Interrupt Service Routine must be ended with the iret instruction. The iret instruction exe- cutes the following operations: – The Flag register is popped from system stack. – If ENCSR is set, CSR is popped from system stack. – The PC high byte is popped from system stack. – The PC low byte is popped from system stack. – All unmasked Interrupts are enabled by setting the CICR.IEN bit. – If ENCSR is reset, CSR is used instead of ISR. Normal program execution thus resumes at the in- terrupted instruction. All pending interrupts remain pending until the next ei instruction (even if it is executed during the interrupt service routine). Note: In Concurrent mode, the source priority level is only useful during the arbitration phase, where it is compared with all other priority levels and with the CPL. No trace is kept of its value during the ISR. If other requests are issued during the inter- rupt service routine, once the global CICR.IEN is re-enabled, they will be acknowledged regardless of the interrupt service routine’s priority. This may cause undesirable interrupt response sequences. 6 5 4 7 Priority Level MAIN CPL is set to 5 CPL=7 MAIN INT 6 CPL=6 INT6 ei CPL is set to 7 CPL6 > CPL5: INT6 pending INTERRUPT 6 HAS PRIORITY LEVEL 6 by MAIN program 9 |
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