ST92F124 datasheet(98/429 Pages) STMICROELECTRONICS

98 / 429 page

98/429

ST92F124/F150/F250 - INTERRUPTS

ARBITRATION MODES (Cont’d)

5.5.2 Nested Mode

The difference between Nested mode and Con-

current mode, lies in the modification of the Cur-

rent Priority Level (CPL) during interrupt process-

ing.

The arbitration phase is basically identical to Con-

current mode, however, once the request is ac-

knowledged, the CPL is saved in the Nested Inter-

rupt Control Register (NICR) by setting the NICR

bit corresponding to the CPL value (i.e. if the CPL

is 3, the bit 3 will be set).

The CPL is then loaded with the priority of the re-

quest just acknowledged; the next arbitration cycle

is thus performed with reference to the priority of

the interrupt service routine currently being exe-

cuted.

Start of Interrupt Routine

The interrupt cycle performs the following steps:

– All maskable interrupt requests are disabled by

clearing CICR.IEN.

– CPL is saved in the special NICR stack to hold

the priority level of the suspended routine.

– Priority level of the acknowledged routine is

stored in CPL, so that the next request priority

will be compared with the one of the routine cur-

rently being serviced.

– The PC low byte is pushed onto system stack.

– The PC high byte is pushed onto system stack.

– If ENCSR is set, CSR is pushed onto system

stack.

– The Flag register is pushed onto system stack.

– The PC is loaded with the 16-bit vector stored in

the Vector Table, pointed to by the IVR.

– If ENCSR is set, CSR is loaded with ISR con-

tents; otherwise ISR is used in place of CSR until

iret

instruction.

Figure 48. Simple Example of a Sequence of Interrupt Requests with:

- Nested mode

- IEN unchanged by the interrupt routines

MAIN

INT 2

INT0

INT4

INT3

INT2

CPL is set to 7

CPL=2

CPL=7

INTERRUPT 2 HAS PRIORITY LEVEL 2

INTERRUPT 3 HAS PRIORITY LEVEL 3

INTERRUPT 4 HAS PRIORITY LEVEL 4

INTERRUPT 5 HAS PRIORITY LEVEL 5

MAIN

INT 3

CPL=3

INT 6

CPL=6

INT5

INT 0

CPL=0

INT6

INT2

INTERRUPT 6 HAS PRIORITY LEVEL 6

INTERRUPT 0 HAS PRIORITY LEVEL 0

CPL6 > CPL3:

INT6 pending

CPL2 < CPL4:

Serviced next

INT 2

CPL=2

INT 4

CPL=4

INT 5

CPL=5

Priority Level of

Interrupt Request

ST92F124 数据表(PDF) 98 Page - STMicroelectronics

ST92F124 数据表(HTML) 98 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载