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ST92F124/F150/F250 - INTERRUPTS

5.7 STANDARD INTERRUPTS (CAN AND SCI-A)

The two on-chip CAN peripherals generate 4 inter-

rupt sources each. The SCI-A interrupts are

mapped on a single interrupt channel. The map-

ping is shown in the following table.

Table 21. Interrupt Channel Assignment

5.7.1 Functional Description

The SIPRL and SIPRH registers contain the inter-

rupt pending bits of the interrupt sources. The

pending bits are set by hardware on occurrence of

a rising edge event. The pending bits are reset by

hardware when the interrupt is acknowledged.

The SIMRL and SIMRH registers are used to

mask the interrupt requests coming from the inter-

rupt sources. Resetting the bits of these registers

prevents the interrupt requests being sent to the

ST9 core.

The SITRL and SITRH registers are used to select

the edge sensitivity of the interrupt channel (rising

or falling edge). As the SCI-A and CAN interrupt

events are rising edge events, all bits in the SITRL

set to 1.

The priority level of the interrupt channels can be

programmed to one of eight priority levels using

the SIPLRL and SIPLRH control registers.

The two MSBs of the priority level are user pro-

grammable. For each interrupt group, the even

channels (E0, F0, G0, H0, I0) have an even priority

level (LSB of priority level is zero) and the odd

channels (E1, F1, G1, H1) have an odd priority lev-

el (the LSB of priority level is one). See Figure 52.

Figure 52. Priority Level Examples

All interrupt channels share a single interrupt vec-

tor register (SIVR). Bits 1 to 4 of the SIVR register

change according to the interrupt channel which

has the highest priority pending interrupt request.

If more than one interrupt channel has pending in-

terrupt requests with the same priority, then an in-

ternal daisy chain decides the interrupt channel

that will be served. INTE0 is first in the internal dai-

sy chain and INTI0 is last.

An overrun flag is associated with each interrupt

channel. If a new interrupt request comes before

the earlier interrupt request is acknowledged then

the corresponding overrun flag is set.

Interrupt Pairs

Interrupt Source

INTE0

INTE1

CAN0_RX0

CAN0_RX1

INTF0

INTF1

CAN0_TX

CAN0_SCE

INTG0

INTG1

CAN1_RX0

CAN1_RX1

INTH0

INTH1

CAN1_TX

CAN1_SCE

INTI0

INTI1

SCI-A

Reserved

PL2H PL1H PL2G PL1G PL2F PL1F PL2E PL1E

INT.G1:

INT.H1: 001=1

INT.G0:

SOURCE

PRIORITY

SOURCE

INT.E0: 010=2

INT.E1: 011=3

INT.F1: 101=5

INT.F0: 100=4

INT.H0: 000=0

IPLRL

100=4

101=5

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