ST92F124 datasheet(105/429 Pages) STMICROELECTRONICS

105 / 429 page

105/429

ST92F124/F150/F250 - INTERRUPTS

Figure 54. Top Level Interrupt Structure

5.10 INTERRUPT RESPONSE TIME

The interrupt arbitration protocol functions com-

pletely asynchronously from instruction flow and

requires 5 clock cycles. One more CPUCLK cycle

is required when an interrupt is acknowledged.

Requests are sampled every 5 CPUCLK cycles.

If the interrupt request comes from an external pin,

the trigger event must occur a minimum of one

INTCLK cycle before the sampling time.

When an arbitration results in an interrupt request

being generated, the interrupt logic checks if the

current instruction (which could be at any stage of

execution) can be safely aborted; if this is the

case, instruction execution is terminated immedi-

ately and the interrupt request is serviced; if not,

the CPU waits until the current instruction is termi-

nated and then services the request. Instruction

execution can normally be aborted provided no

write operation has been performed.

For an interrupt deriving from an external interrupt

channel, the response time between a user event

and the start of the interrupt service routine can

range from a minimum of 26 clock cycles to a max-

imum of 55 clock cycles (DIV instruction), 53 clock

cycles (DIVWS and MUL instructions) or 49 for

other instructions.

For a non-maskable Top Level interrupt, the re-

sponse time between a user event and the start of

the interrupt service routine can range from a min-

imum of 22 clock cycles to a maximum of 51 clock

cycles (DIV instruction), 49 clock cycles (DIVWS

and MUL instructions) or 45 for other instructions.

In order to guarantee edge detection, input signals

must be kept low/high for a minimum of one

INTCLK cycle.

An interrupt machine cycle requires a basic 18 in-

ternal clock cycles (CPUCLK), to which must be

added a further 2 clock cycles if the stack is in the

added if the CSR is pushed (ENCSR =1).

The interrupt machine cycle duration forms part of

the two examples of interrupt response time previ-

ously quoted; it includes the time required to push

values on the stack, as well as interrupt vector

handling.

In Wait for Interrupt mode, a further cycle is re-

quired as wake-up delay.

WATCHDOG ENABLE

WDGEN

WATCHDOG TIMER

END OF COUNT

NMI

TLTEV

MUX

TLIS

TLIP

TLNM

TLI

IEN

PENDING

MASK

TOP LEVEL

INTERRUPT

VA00294

CORE

RESET

REQUEST

ST92F124 数据表(PDF) 105 Page - STMicroelectronics

ST92F124 数据表(HTML) 105 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载