ST92F124 datasheet(61/429 Pages) STMICROELECTRONICS

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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM)

3.5 PROTECTION STRATEGY

The protection bits are stored in the 4 locations

from 231FFCh to 231FFFh (see Figure 34).

All the available protections are forced active dur-

ing reset, then in the initialisation phase they are

read from the TestFlash.

The protections are stored in 2 Non Volatile Regis-

ters. Other 2 Non Volatile Registers can be used

as a password to re-enable test modes once they

have been disabled.

The protections can be programmed using the Set

Protection operation (see Control Registers para-

graph), that can be executed from all the internal

or external memories except the Flash or Test-

Flash itself.

The TestFlash area (230000h to 231F7Fh) is al-

ways protected against write access.

Figure 34. Protection Register Map

3.5.1 Non Volatile Registers

The 4 Non Volatile Registers used to store the pro-

tection bits for the different protection features are

one time programmable by the user.

Access to these registers is controlled by the pro-

tections related to the TestFlash. Since the code to

program the Protection Registers cannot be

fetched by the Flash or the TestFlash memories,

this means that, once the APRO or APBR bits in

the NVAPR register are programmed, it is no long-

er possible to modify any of the protection bits. For

this reason the NV Password, if needed, must be

set with the same Set Protection operation used to

program these bits. For the same reason it is

strongly advised to never program the WPBR bit in

the NVWPR register, as this will prevent any fur-

ther write access to the TestFlash, and conse-

quently to the Protection Registers.

NON VOLATILE ACCESS PROTECTION REG-

ISTER (NVAPR)

Address: 231FFCh - Read/Write

Delivery value: 1111 1111 (FFh)

Bit 7 = Reserved.

Bit 6 = APRO: FLASH access protection.

This bit, if programmed at 0, disables any access

(read/write) to operands mapped inside the Flash

address space (E3 TM excluded), unless the current

instruction is fetched from the TestFlash or from

the Flash itself.

0: ROM protection on

1: ROM protection off

Bit 5 = APBR: TestFlash access protection.

This bit, if programmed at 0, disables any access

(read/write) to operands mapped inside the Test-

Flash, the OTP and the protection registers, un-

less the current instruction is fetched from the

TestFlash or the OTP area.

0: TestFlash protection on

1: TestFlash protection off

Bit 4 = APEE: E3 TM access protection.

This bit, if programmed at 0, disables any access

(read/write) to operands mapped inside the E3 TM

address space, unless the current instruction is

fetched from the TestFlash or from the Flash, or

from the E3 TM itself.

0: E3 TM protection on

1: E3 TM protection off

Bit 3 = APEX: Access Protection from External

memory.

This bit, if programmed at 0, disables any access

(read/write) to operands mapped inside the ad-

dress space of one of the internal memories (Test-

Flash, Flash, E3 TM, RAM), if the current instruction

is fetched from an external memory.

0: Protection from external memory on

1: Protection from external memory off

NVAPR

NVWPR

231FFCh

231FFDh

231FFEh

NVPWD0

NVPWD1

231FFFh

765

432

APRO APBR

APEE

APEX

PWT2 PWT1 PWT0

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