ST92F124 datasheet(184/429 Pages) STMICROELECTRONICS

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EXTENDED FUNCTION TIMER (EFT)

EXTENDED FUNCTION TIMER (Cont’d)

CONTROL REGISTER 1 (CR1)

R252 - Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = ICIE Input Capture Interrupt Enable.

0: Interrupt enabling depends on the IC1IE and

IC2IE bits in the CR3 register.

1: An interrupt is generated whenever the ICF1 or

ICF2 bit in the SR register is set. The IC1IE and

IC2IE bits in the CR3 register do not have any

effect in this case.

Bit 6 = OCIE Output Compare Interrupt Enable.

0: Interrupt generation depends on the OC1IE and

OC2IE bits in the CR3 register.

1: An interrupt is generated whenever the OCF1 or

OCF2 bit in the SR register is set. The OC1IE

and OC2IE bits in the CR3 rgister do not have

any effect in this case.

Bit 5 = TOIE Timer Overflow Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is enabled whenever the TOF

bit of the SR register is set.

Bit 4 = FOLV2 Forced Output Compare 2.

0: No effect.

1: Forces the OLVL2 bit to be copied to the

OCMP2 pin.

Bit 3 = FOLV1 Forced Output Compare 1.

0: No effect.

1: Forces OLVL1 to be copied to the OCMP1 pin.

Bit 2 = OLVL2 Output Level 2.

This bit is copied to the OCMP2 pin whenever a

successful comparison occurs with the OC2R reg-

ister and OC2E is set in the CR2 register. This val-

ue is copied to the OCMP1 pin in One Pulse Mode

and Pulse Width Modulation mode.

Bit 1 = IEDG1 Input Edge 1.

This bit determines which type of level transition

on the ICAP1 pin will trigger the capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

Bit 0 = OLVL1 Output Level 1.

The OLVL1 bit is copied to the OCMP1 pin when-

ever a successful comparison occurs with the

OC1R register and the OC1E bit is set in the CR2

ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

ST92F124 数据表(PDF) 184 Page - STMicroelectronics

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