ST92F124 datasheet(223/429 Pages) STMICROELECTRONICS

223 / 429 page

223/429

MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)

MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.5.10 Interrupts and DMA

10.5.10.1 Interrupts

The SCI can generate interrupts as a result of sev-

eral conditions. Receiver interrupts include data

pending, receive errors (overrun, framing and par-

ity), as well as address or break pending. Trans-

mitter interrupts are software selectable for either

Transmit Buffer Register Empty (BSN set) or for

Transmit Shift Register Empty (BSN reset) condi-

tions.

Typical usage of the Interrupts generated by the

SCI peripheral are illustrated in Figure 116.

The SCI peripheral is able to generate interrupt re-

quests as a result of a number of events, several

of which share the same interrupt vector. It is

therefore necessary to poll S_ISR, the Interrupt

Status Register, in order to determine the active

trigger. These bits should be reset by the program-

mer during the Interrupt Service routine.

The four major levels of interrupt are encoded in

hardware to provide two bits of the interrupt vector

er vectors to be resolved to an 8 byte block size.

The SCI interrupts have an internal priority struc-

ture in order to resolve simultaneous events. Refer

also to Section 10.5.4 SCI-M Operating Modes for

more details relating to Synchronous mode.

Table 47. SCI Interrupt Internal Priority

Receive DMA Request

Highest Priority

Transmit DMA Request

Receive Interrupt

Transmit Interrupt

Lowest Priority

ST92F124 数据表(PDF) 223 Page - STMicroelectronics

ST92F124 数据表(HTML) 223 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载