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ST92F124 数据表(PDF) 238 Page - STMicroelectronics |
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ST92F124 数据表(HTML) 238 Page - STMicroelectronics |
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238 / 429 page  238/429 ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A) ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 117. SCI-A Block Diagram WAKE UP UNIT RECEIVER CONTROL SCISR TRANSMIT CONTROL TDRE TC RDRF IDLE OR NF FE PE SCI CONTROL INTERRUPT SCICR1 R8 T8 SCID M WAKE PCE PS PIE Received Data Register (RDR) Received Shift Register Read Transmit Data Register (TDR) Transmit Shift Register Write RDI TDO (DATA REGISTER) SCIDR TRANSMITTER CLOCK RECEIVER CLOCK RECEIVER RATE TRANSMITTER RATE SCIBRR SCP1 fCPU CONTROL CONTROL SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0 /PR /16 CONVENTIONAL BAUD RATE GENERATOR SBK RWU RE TE ILIE RIE TCIE TIE SCICR2 Extended Prescaler Block Diagram LINE - SCICR3 - -- - - - (cf.Figure 119) 9 |
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