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PCF5083H/5V2/F3 数据表(PDF) 58 Page - NXP Semiconductors |
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PCF5083H/5V2/F3 数据表(HTML) 58 Page - NXP Semiconductors |
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58 / 136 page  1996 Oct 29 58 Philips Semiconductors Objective specification GSM signal processing IC PCF5083 9.1.6 SYSTEM CONTROLLER INTERFACE The PCF5083 parallel port is used for communication with the P90CL301 System Controller (SC) which is compatible with the 68000 family microcontrollers. Details about interfacing are described in Chapter 10. The host port of the DSP has three internal registers: 1. PI; 16-bit parallel input register (write-only) 2. PO; 16-bit parallel output register (read-only) 3. PIOS; 5-bit parallel I/O Status/Control register (see Table 50). The 16-bit words of registers PI and PO are transferred in two access cycles of 8-bits. The LOW byte/HIGH byte selection is controlled with HA0 and with bit 5 of the PIOS register, PLSB. For correct interrupt generation the transfer order should be HA1 and HA0 = 00; then HA1 and HA0 = 01 (see Table 48). Table 48 Host port register addressing Table 49 Status/Control Register (PIOS) Table 50 Description of PIOS bits PLSB HA1 HA0 DESCRIPTION STATUS REGISTER PIOS CHANGE 0 (1) 0 0 access PI/PO HIGH (LOW) byte no change 0 (1) 0 1 access PI/PO LOW (HIGH) byte PISE = 0 or POSF = 0 X 1 0 reserved no change X 1 1 read status register PIOS no change 76543210 −−− PLSB PORQEN PIRQEN POSF PISE BIT NAME DIRECTION DESCRIPTION 7 −− These three bits are not used. 6 −− 5 −− 4 PLSB read This bit controls the parallel transfer order. When PLSB = 1; the LSB is transferred first. The reset value is a logic 1. 3 PORQEN read/write When PORQEN = 1; PORQN is enabled. The reset value is a logic 0. 2 PIRQEN read/write When PIRQEN = 1; PIRQN is enabled. The reset value is a logic 0. 1 POSF read When POSF = 1; the Output Register (PO) is full. The reset value is a logic 0. 0 PISE read When PISE = 1; the Input Register (PI) is empty. The reset value is a logic 1. |
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