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PCF5083H/5V2/F3 数据表(PDF) 2 Page - NXP Semiconductors |
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PCF5083H/5V2/F3 数据表(HTML) 2 Page - NXP Semiconductors |
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2 / 136 page ![]() 1996 Oct 29 2 Philips Semiconductors Objective specification GSM signal processing IC PCF5083 CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 3 APPLICATIONS 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING INFORMATION 6.1 Pinning 6.2 Pinning description 7 OVERVIEW OF THE GSM CHIP SET 7.1 General 7.2 The role of the PCF5083 8 FUNCTIONAL DESCRIPTION TIMER CORE 8.1 Clock generator 8.2 ON/OFF Logic 8.2.1 Mobile switch-on procedure 8.2.2 Mobile switch-off procedure 8.2.3 OFF/Watchdog Timer 8.3 Timing Generator 8.3.1 The Quarterbit Counter 8.3.2 Normal Mode 8.3.3 Sleep Mode 8.4 RF-IC Interface Bus 8.4.1 Frequency Setting Channel 8.4.2 Gain Control Channel 8.4.3 Immediate Control Channel 8.4.4 Operation Modes and Control Registers 8.5 IOM®-2 Interface 8.5.1 IOM®-2 Clock Generation 8.5.2 IOM®-2 Master Unit 8.5.3 Monitor Channel Transmitter Protocol 8.5.4 Monitor Channel Receiver Protocol 8.5.5 Command/Indication Channel Transmitter 8.5.6 Command/Indication Channel Receiver 8.5.7 Audio Interface 8.5.8 External IOM®-2 Interface 8.6 MMI Interface 8.6.1 RS232 Interface 8.6.2 MMI power-down Interface 8.7 General purpose parallel I/O-port 8.8 Real Time Clock 8.8.1 Setting the real time clock 9 DESCRIPTION OF THE DSP CORE 9.1 Interface description 9.1.1 Baseband Digitizer Interface 9.1.2 GMSK Modulator Interface 9.1.3 Audio and Data Interface 9.1.4 Audio interface 9.1.5 Terminal adaptor interface for data services 9.1.6 System controller interface 9.1.7 Event Counter Clock 9.1.8 Usage of General Purpose I/O Pins 9.1.9 Power saving modes 9.2 Message Interface to the System Controller 9.2.1 Execution of GSM baseband procedures 9.2.2 No Operation (NOP) command 9.2.3 Soft resetting the DSP 9.2.4 Error handling 9.3 GSM baseband procedures 9.3.1 Procedure description 9.3.2 Performance of GSM baseband procedures 9.4 Software applications 9.4.1 Receiving a CCH block 9.4.2 Transmitting a CCH block 9.4.3 FB search for timing synchronization 9.4.4 Processing a TCH/FS multiframe 10 MICROCONTROLLER INTERFACE 10.1 Register Set for the Timer Core 10.2 Interrupt Logic 11 RESET 12 JTAG TEST INTERFACE 13 TEST AND EMULATION MODES 14 LIMITING VALUES 15 DC CHARACTERISTICS 16 AC CHARACTERISTICS 17 APPLICATION INFORMATION 18 PACKAGE OUTLINE 19 SOLDERING 19.1 Introduction 19.2 Reflow soldering 19.3 Wave soldering 19.4 Repairing soldered joints 20 DEFINITIONS 21 LIFE SUPPORT APPLICATIONS |
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