PCF5083HSLASH5V2SLASHF3 datasheet(21/136 Pages) PHILIPS

21 / 136 page

1996 Oct 29

Philips Semiconductors

Objective speciﬁcation

GSM signal processing IC

PCF5083

8.3.1

THE QUARTERBIT COUNTER

The quarterbit counter (QBC) represents the timebase of

the mobile. It consists of a 13-bit upcounter. The counter

directly counts the quarterbit steps within one TDMA

frame. Its range is therefore 0 to 4999.

At the beginning of every TDMA frame (quarterbit counter

state 0) the signal FRAME_INT goes LOW, generating an

interrupt (frame interrupt) to the System Controller. The

interrupt line is deactivated by accessing the register

MODE0_REG. The frame interrupt is disabled with

MODEx_REG[DISFRAMEINT] = 1.

8.3.1.1

Initial Quarterbit Counter Timing Alignment

The timing offset between a base station and a mobile

station can be corrected by presetting the quarterbit

counter with an estimated correction value. Therefore the

value in frame N and the flag QBRCTRL_REG[SYNC] has

to be set.

At the end of frame N the quarterbit counter is loaded from

QBC_REG with zeros. The duration of frame N + 1 is

5000

− [QBC_REG] and the mobile will be synchronised at

the beginning of frame N + 2. The frame interrupt at the

beginning of frame N + 1 is disabled. The timing

generation is disabled during frame N + 1. The SYNC flag

is cleared after synchronization.

For the System Controller the resulting timing looks like

frame N being extended and synchronization being

achieved with frame N + 1.

8.3.1.2

Maintaining the Quarterbit Counter Timing

Alignment

Small timing corrections can be made by inserting or

extracting one quarterbit step at the beginning of a TDMA

frame. Therefore the INSERT or EXTRACT flag in register

QBCCTRL_REG have to be set. These flags are cleared

after the timing alignment was performed.

8.3.2

NORMAL MODE

In Normal mode the Timing Generator provides the output

signals speciﬁed in Table 8.

The power-down signals NPDTX2, NPDTX1 and

NPDBIAS are active LOW by default. All other signals are

active HIGH by default. Active HIGH in this context means

that the signals are on high level during a receive or a

transmit burst.

The output polarity can be changed by setting the

corresponding bit in register POL_REG to a logic 1. The

signals can be clamped to a level depending on their flag

in POL_REG by setting the corresponding bit in register

MASK_REG to a logic 0.

After a reset with RST, the receiver, transmitter and

synthesizer control lines are set to their inactive level.

The general MS timing is assumed to have the receive

timeslot (RX) in timeslot 0, the transmit timeslot (TX) in

timeslot 3 and the monitor timeslot (MON) in timeslot 6

within a TDMA frame.

Table 8

Output signals

SIGNAL

DESCRIPTION

Signals for the receiver section

RXON

baseband interface IC receiver enable

BEN

baseband interface IC enable

PDRX1

receiver power-down 1

PDRX2

receiver power-down 2

Signals for the transmitter section

TXON

baseband interface IC transmitter enable

BEN

baseband interface IC enable

TXKEY1

power ampliﬁer power-down

TXKEY2

power ramping controller trigger signal

PDTX1

transmitter power-down 1

NPDTX1

inverted output of PDTX1

NPDTX2

transmitter power-down 2

PDPIAS

power ampliﬁer bias voltage power-down

NPDBIAS

inverted output of PDBIAS

Signal for the synthesizer

PDSYN

synthesizer power-down

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