PCF5083HSLASH5V2SLASHF3 datasheet(31/136 Pages) PHILIPS

31 / 136 page

1996 Oct 29

Philips Semiconductors

Objective speciﬁcation

GSM signal processing IC

PCF5083

8.3.3.3

Sleep Clock Calibration

Since the ratio between the quarterbit clock and the sleep

clock may vary, an accurate value for the increment

SQBC_INC can be obtained with the following procedure:

1. Set QBCCTRL_REG[CAL] = 1 to enable the

calibration mode.

2. The calibration procedure lasts for 8 seconds.

3. After calibration, the CAL flag in QBCCTRL_REG is

automatically cleared. After 1 ms the register

SQBCINC_REG holds the lower 8 bits of the

increment value and can be used to verify the

calibration process. The maximum allowed frequency

deviation is

−23.8 kHz to +25.4 kHz at 13 MHz and

−63.6 Hz to +60.3 Hz at 32.768 kHz.

During the calibration procedure, the 13 MHz master clock

may not be switched off. Therefore, REFON stays active

even if the Sleep mode is enabled.

The calibration procedure has to be repeated from time to

time, because the exact frequency of the 13 MHz as well

as the 32 kHz clock may change.

After power up, the calibration procedure must be

performed before the Sleep mode can be activated.

8.3.3.4

Reduced Sleep mode

During reduced Sleep mode the mobile timing is

maintained with the quarterbit counter. The sleep

quarterbit counter is not used. For the System Controller

all timings are as in Sleep mode. The signal REFON is

always active. All other Sleep mode signals (GPON1 etc.)

are activated as during Sleep mode. The reduced Sleep

mode is invoked with QBCCTRL_REG[SLEEP] = 1 and

QBCCTRL_REG[SLEEPRED] = 1.

8.3.3.5

From Sleep mode to Normal mode

The PCF5083 is forced into a wake-up state if the

hardware control interrupt HWCTRL_INT is asserted

internally (caused by the ON/OFF monitor, MMI

power-down unit or real time clock). The interrupt line

COMB_INT is not asserted but the interrupt stays pending

internally until Sleep mode is finished.

If the PCF5083 enters the wake-up state and

SLEEPCNT_REG is less than or equal to REFON_REG,

the Sleep mode terminates normally. Otherwise, if

SLEEPCNT_REG is greater than REFON_REG,

REFON_REG is copied to SLEEPCNT_REG instead of

SLEEPCNT_REG being decremented at the next frame

boundary and the Sleep mode terminates with reduced

duration. The maximum delay from any wake-up request

to the end of the wake-up procedure depends on the

setting of REFON_REG and is 64

× 4.6 ms = 294.4 ms.

After entering the normal mode again FRAMECNT_REG

shows the number of actually slept frames. If the Sleep

mode terminated normally, this number equals the number

SLEEPCNT_REG previously was programmed with.

The System Controller now has to set up the timing

generator mode for the next frame. With the beginning of

the next frame the PCF5083 enters the normal operation

again.

PCF5083H/5V2/F3 数据表(PDF) 31 Page - NXP Semiconductors

PCF5083H/5V2/F3 数据表(HTML) 31 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载