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PCF5083H/5V2/F3 数据表(PDF) 17 Page - NXP Semiconductors |
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PCF5083H/5V2/F3 数据表(HTML) 17 Page - NXP Semiconductors |
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17 / 136 page  1996 Oct 29 17 Philips Semiconductors Objective specification GSM signal processing IC PCF5083 8.2 ON/OFF Logic The ON/OFF logic performs the main power on and off switching function for the whole mobile. The on/off conditions are controlled via an operators keyboard, a low voltage battery indication circuit, a hardware Watchdog Timer or an auxiliary switch on input for general purpose use. The hardware control interrupt HWCTRL_INT, signalled via the COMB_INT output (refer to Section 10.2), is used to signal the status of the ON/OFF Logic. The inputs DSPEN and TIMEN are used to control the Watchdog function. RST and RSTO are asynchronous reset lines. The inputs ONKEY, AUXON and LOWVOLT are debounced with a time constant of 62.5 ms. The minimum pulse width for the safe detection of a signal transition is therefore 2 × 62.5 = 125 ms on any of these lines. The ON/OFF Logic signals are specified in Table 4. Table 4 ON/OFF Logic signals SIGNAL DESCRIPTION ONKEY Input (active HIGH) to be connected to the ON/OFF switch of the operators keyboard. AUXON Input (edge sensitive) for general purpose use, e.g. used as battery charger connect indication or ignition sense in mobile applications. LOWVOLT Input (active LOW) to be connected to an external low battery indication circuit. POWON Output (active HIGH) to be connected to the ON terminal of the supply voltage switch. NPOWON Inverted output signal of POWON. 8.2.1 MOBILE SWITCH-ON PROCEDURE Switching on the mobile is initiated via the PCF5083 according to Table 5. If one of the three conditions ONKEY, AUXON or Alarm time match become true, a corresponding flag is set in register HWCTRL_REG. As soon as one of these flags is set, signal POWON is set and NPOWON is reset. At the same time the HWCTRL_INT interrupt is activated. The interrupt condition is signalled via the COMB_INT line to the System Controller if the relevant bit is set in the COMBINT_REG register (refer to Section 10.2). The hardware reset RST clears the enable bits for the COMB_INT interrupt lines. The interrupt flags in register HWCTRL_REG must be cleared by the System Controller to deactivate the interrupt condition. A flag is cleared by writing a logic 1 to its bit location. The POWON output is the main power control signal. As soon as POWON goes HIGH, all ICs in the mobile are powered via the supply voltage switch. The LOWVOLT input asserted LOW, indicating a low voltage situation, or RSTO asserted LOW inhibits the mobile to be switched on. If the PCF5083 was switched on via AUXON (HWCTRL_REG[AUXON_LH] = 1) and the AUXON signal remains HIGH, the flag HWCTRL_REG[AUXON_LH] must be cleared, before the PCF5083 enters the Power-down mode. Table 5 Mobile switch-on conditions RST0 LOWVOLT ONKEY AUXON ALARM TIME MATCHES CURRENT TIME POWON COMB_INT L X X X X L 3-state H L X X X L 3-state HH L ¡ HX X L ¡ HH ¡ L HH X L ¡ HX L ¡ HH ¡ L H H X X yes L ¡ HH ¡ L |
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