PCF5083HSLASH5V2SLASHF3 datasheet(60/136 Pages) PHILIPS

60 / 136 page

1996 Oct 29

Philips Semiconductors

Objective speciﬁcation

GSM signal processing IC

PCF5083

9.1.9

POWER SAVING MODES

9.1.9.1

Idle mode

When operating in Idle mode the DSP enters a dormant

state and requires only a fraction of the power normally

needed to supply the device in the full operating mode.

The processor core is switched off whereas the I/O section

of the processor is fully functional. The Idle mode is

invoked by the on-chip firmware whenever the DSP is

waiting for an I/O event. The DSP automatically leaves the

Idle mode as soon as the input or output operation has

been completed.

9.1.9.2

Power-down mode

The Power-down mode is initiated when the signal

DSPON is deactivated during Sleep mode (see

Section 8.3.3). The DSP will stop operation synchronously

after a maximum of 3 CLKI cycles delay. All parts of the

DSP which operate with the main processor clock are in

static state. Only the blocks running with the serial

interface clocks are not affected by the Power-down mode.

For minimum power consumption the external serial shift

clocks should therefore be switched off. The DSP remains

in the power-down state as long as the signal DSPON is

held inactive. The processor continues its operation for a

maximum of 3 clock cycles after the signal DSPON is set

active again.

9.2

Message Interface to the System Controller

The DSP can be controlled with commands and joining

16-bits parameters from the System Controller via the host

port register PI. The first word always contains the

command OPCODE and length. The second word is an

arbitrary ID code which is useful for debugging purposes.

The following words are command parameters. The DSP

can also generate indications giving status information or

requested data. These indication messages can be read

(R) via host port register PO.

The DMA message is used to download data into the

program/data RAM. Download is always done into the

data address space. The parameters mc_before and

mc_after indicate the value of the Memory Configuration

switch a RAM bank into the data address space, download

a program and switch it back afterwards. For more

information about the MC Register and the PCF5083

memory mapping please refer to

“Information Manual

Digital Signal Processors PCF508x, Philips

Semiconductors, 1995”.

Table 52 Commands/indications to/from the PCF5083

Note

1. X = don’t care.

MNEMONIC

DIRECTION

OPCODE(1)

bit 15 to bit 8

LENGTH

bit 7 to bit 0

DATA

DMA

write

0X0000

msg_id

mc_before n_words;

address data [1] to data [n words];

mc_after

EXEC_PROC

write

0X01

3 + npar

msg_id

proc_id;

parameter_1 to parameter_N

PROC_RETUR

read

0X11

3 + n_retvals

msg_id

proc_id;

return_value 1 to return value_N

PACKET

write

0X02

2 + N (cmd_len)

msg_id

cmd_1 to cmd_N

RESET

write

0X03

msg_id

reset_parm

NOP

write

0X05

2 + N

msg_id

data_1 to data_N

ERROR

read

0X12

msg_id

error_code

PCF5083H/5V2/F3 数据表(PDF) 60 Page - NXP Semiconductors

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