PCF5083HSLASH5V2SLASHF3 datasheet(99/136 Pages) PHILIPS

99 / 136 page

1996 Oct 29

Philips Semiconductors

Objective speciﬁcation

GSM signal processing IC

PCF5083

10 MICROCONTROLLER INTERFACE

The PCF5083 includes a standard 68000 compatible microcontroller interface. The interface consists of the lines

specified in Table 76.

The 128-byte wide register space of the Timer core is selected if HCEN_T is asserted. The 4 byte wide register space

of the DSP core is selected if HCEN_D is asserted. The DSP core only uses the address lines HA0 and HA1. All other

address lines are don’t care for the DSP core.

The Timer core accessed via HCEN_T does not assert DTACK.

Registers wider than 8-bit are aligned on word boundaries with the MSB on the lowest address and the LSB on the

highest address. For registers which use only three byte addresses, a reserved address location is provided to make

these registers accessible as longwords.

Reserved address locations, write only bits or registers and unused bits within registers are read as zeros and don’t care

for write operations.

For the DSP Core refer to Section 9.1.6.

Table 76 The Interface signal lines

10.1

Table 77 Register set

SIGNAL

DESCRIPTION

HD0 to HD7

8-bit bidirectional data bus.

HA0 to HA6

7-bit unidirectional address bus.

HR/W

Read/write select line. A logic 0, writes to the PCF5083. A logic 1, reads from the PCF5083.

HCEN_T

Chip select line for the Timer core (active LOW).

HCEN_D

Chip select line for the DSP core (active LOW).

DTACK

DSP core data acknowledge line (connected to the DTACK input of a 68000 compatible

microcontroller.

OFFSET

SIZE

R/W(1)

DESCRIPTION

00, 01

MODE0_REG

R/W

Mode Control Register 0; see Table 78

02, 03

MODE1_REG

R/W

Mode Control Register 1; see Table 78

RXBURST0_REG

RXON length in bit

RXBURST1_REG

RXON length in bit

RXBURST2_REG

RXON length in bit

TXBURST0_REG

TXON length in bit

TXBURST1_REG

TXON length in bit

TXBURST2_REG

Start of the Rx burst in QB

0A, 0B

TXSTART_REG

Start of the TX burst in QB

0C, 0D

MONSTART_REG

Start of the MON burst in QB

0E, 0F

TXKEY0_REG

TXKEY0 length in QB

10, 11

TXKEY1_REG

TXKEY1 length in QB

GPON1_REG

Time of GPON1 getting active in TDMA frames before the end

of the Sleep mode

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