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PCF5083H/5V2/F3 数据表(PDF) 100 Page - NXP Semiconductors |
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PCF5083H/5V2/F3 数据表(HTML) 100 Page - NXP Semiconductors |
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100 / 136 page  1996 Oct 29 100 Philips Semiconductors Objective specification GSM signal processing IC PCF5083 13 GPON2_REG 6 W Time of GPON2 getting active in TDMA frames before the end of the Sleep mode 14 reserved −− − 15 DSPON_REG 6 W Time of DSPON getting active in TDMA frames before the end of the Sleep mode 16 REFON_REG 6 W Time of (N)REFON getting active in TDMA frames before the end of the Sleep mode 17 PDRX1_REG 5 W Time of PDRX1 getting active in 32 QB before RXON active 18 PDRX2_REG 5 W Time of PDRX2 getting active in 32 QB before RXON active 19 PDTX1_REG W Time of PDTX1 getting active in 32 QB before TXON active 1A PDTX2_REG W Time of NPDTX2 getting active in 32 QB before TXON active 1B PDBIAS_REG W Time of PDBIAS getting active in 32 QB before TXON active 1C PDSYN_REG W Time of PDSYN getting active in 32 QB before RXON/TXON active 1D AGCSTART_REG W Time of DACON_REG to be sent in 32 QB before RXON active 1E PDDELAY_REG 6 W PDTX1, NPDTX2 and PDSYN inactive to TXKEY1 inactive delay in QB 1F KEYOFF_REG 6 W TXKEY2 inactive to TXKEY1 inactive delay in QB 20, 21 KEYON2_REG 9 W TXKEY2 active to TXON active delay in QB 22, 23 KEYON1_REG 9 W TXKEY1 active to TXON active delay in QB 24, 25 POL_REG 14 R/W Polarity of Power-Down Control Lines; see Table 79 26, 27 MASK_REG 15 R/W Bit mask register for Power-Down Control Lines; see Table 80 28 QBCCTRL_REG 8 R/W Quarterbit counter control register; see Table 81 29 SQBCINC_REG 8 R Sleep quarterbit counter increment STOP_REG 8 W Stop OFF-Timer with data value A5H 2A, 2B QBC_REG 15 R QBC access for synchronization 13 W R: read 15-bit quarterbit counter (1 ⁄4 QB resolution) W: write 13-bit synchronization value (1 QB resolution) 2C, 2D SLEEPCNT_REG 9 W Number of TDMA frames to sleep FRAMECNT_REG 9 R Duration of last Sleep mode period in TDMA frames 2E, 2F HWCTRL_REG 11 R/W Hardware Control Register; see Table 82 30 to 3F −− R/W Real Time Clock registers; see Table 83 3E reserved −− − 3F to 41 RX_REG 17 W RF Bus: RX frequency 42 reserved −− − 43 to 45 TX_REG 17 W RF Bus: TX frequency 46 reserved −− − 47. to 49 MON_REG 17 W RF Bus: MON frequency 4A reserved −− − 4B to 4D RXGAIN_REG 18 W RF Bus: RX gain 4E reserved −− − 4F to 51 TXGAIN_REG 18 W RF Bus: Gain setting for a MON burst during the TX timeslot OFFSET REGISTER SIZE R/W(1) DESCRIPTION |
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