PCF5083HSLASH5V2SLASHF3 datasheet(37/136 Pages) PHILIPS

37 / 136 page

1996 Oct 29

Philips Semiconductors

Objective speciﬁcation

GSM signal processing IC

PCF5083

8.5.1

IOM®-2 CLOCK GENERATION

If the IOM®-2 clock and frame synchronization signals are

generated internally from the 13 MHz reference clock, the

basis clock runs at 1.536 MHz as illustrated in Fig.14. One

125

µs FSC period consists of 192 DCL periods (0 to 191).

The DCL periods 12, 25, 38, 51, 64, 77, 90, 103, 116, 129,

142, 155, 168 and 181 are 8T wide (high time = low

time = 4T), where T is the 13 MHz clock period

(T = 77 ns). All other DCL periods are 8.5T wide

(high time = 4.5T, low time = 4T).

It is possible to extend or to reduce 12 consecutive IOM®-2

frame periods by 1T each. This results in a total reduction

or extension of one quarterbit (12T = 923 ns), which is

required in case of timing alignment. This adjustment is

performed by setting either the FSCEXT flag for extension,

or the FSCRED flag for reduction. Both these flags reside

in QCCTRL_REG. The flags are automatically reset after

the adjustment.

The length of the frame synchronization pulse (FSC) is

chosen to 29

× 8.5T + 2 × 8T + 6T = 268.5T.

The whole IOM®-2 signal generation is disabled in Clock

mode 0 (see Table 23, default after reset).

In Sleep mode the REFON output stays active to keep the

13 MHz oscillator running as long as the IOM®-2 interface

is not disabled (Clock mode 0).

Other clock modes are derived from this mode by

subdividing the 1.536 MHz DCL clock by 2, 3, 4, 6, or 12.

The FSC period is not changed.

In external clock mode the IOM®-2 clock and frame

synchronization signal are provided via the DCL and FSC

pins. The DCL clock in this mode is a multiple of 128 kHz

or 256 kHz with a maximum frequency of 2.048 MHz or

4.096 MHz respectively.

In both internal and external clock modes, it is possible to

select between a double clock cycle mode per data bit or

a single clock cycle mode per data bit with the

IOMCON_REG[DATA_MODE] flag. In double clock cycle

mode the data output gets valid with the first rising edge of

DCL and the data input is sampled with the second

negative edge of DCL within a bit period. In single clock

cycle mode the data output gets valid with the rising edge

of DCL and the data input is sampled with the falling edge

of DCL within a bit period. Data is organized in 16-bit

timeslots. The maximum number of timeslots supported is

12 in internal and 16 in external clock mode.

Table 23 lists all possible clock modes.

Table 23 IOM®-2 Clock Modes

DCL

FREQUENCY

SINGLE(1)/DOUBLE(2)

CLOCK CYCLE MODE

NUMBER OF

16-BIT TIMESLOTS

DIVISION

RATIO

CLOCK_MODE

FLAGS (DEC.)

DATA_MODE

FLAG

IOM®-2 interface off

−−

−

1.536 MHz

768 kHz

512 kHz

384 kHz

256 kHz

128 kHz

external clock

× 128 kHz

(2.084 MHz max.)

≤ 16)

−

external clock

× 256 kHz

(4.096 MHz max.)

≤ 16)

−

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