PCF5083HSLASH5V2SLASHF3 datasheet(14/136 Pages) PHILIPS

14 / 136 page

1996 Oct 29

Philips Semiconductors

Objective speciﬁcation

GSM signal processing IC

PCF5083

FUNCTIONAL DESCRIPTION TIMER CORE

8.1

Clock generator

The Clock Generator consists of a low swing input buffer

for the 13 MHz reference clock, a PLL as frequency

multiplier and a 32.768 kHz crystal oscillator. The PLL

generates 13 MHz, 39 MHz and 52 MHz from the 13 MHz

reference clock. The PLL reset input RSTP is used to bring

the PLL into a low-power state when set to a LOW level.

The 13 MHz reference clock is AC coupled to input CKI.

CKI is a reduced swing input which requires a signal in the

range of 0.7 V(p-p) (worst case) for operation. The clock

signal is amplified and used as the input clock for the PLL.

The Timer core is either clocked with the 13 MHz

reference clock or the 13 MHz PLL output. The clock

source is selected with input CLKSEL as shown in Table 1.

Table 1

Timer Core clock selection

CLKSEL

TIMER CORE CLOCK

PLL output

buffered CKI input

Using the PLL output reduces the tolerance requirements

for the duty cycle of the reference clock.

The DSP core will function with the 39 MHz PLL clock or

the clock supplied from DCLK. The clock source is

selected with the flags in SYSCON_REG; see Tables 2

and 3. Within the DSP core the selected clock is first

halved before use. The 52 MHz PLL is register selectable

for future applications but should not be used in the current

implementation of this device

The inverting buffer stage between CLK32I and CLK32O,

together with an external crystal network generates a

32.768 kHz clock for the Timer Core. This clock is used for

the real time clock, the ON/OFF logic etc.

The internal 13 MHz, 19.5 MHz and 2b/2c: 32.768 kHz/

3: 26 MHz clocks are externally available for other system

components, e.g. the microcontroller. All clock outputs can

be disabled if they are not used to reduce the power

consumption.

Table 2

System Conﬁguration Register (SYSCON); note 1

Note

1. Default value after reset 0X00 0000b (x: LOCK is undefined).

2. Versions PCF5083-2b and PCF5083-2c only.

3. PCF5083-3 only.

BIT

FLAG

R/W

DESCRIPTION

−−

Reserved

LOCK

PLL lock select. If LOCK = 0; then PLL in lock. If LOCK = 1; then PLL out of

lock.

RS232_CLK

RS232 interface clock source. If RS232_CLK = 0; then the 13 MHz Timer

clock is used. If RS232_CLK = 1; then the RS232 clock is supplied via the ADI

pin (pin 125).

DSP_CLK1

DSP clock select. This two bits select the DSP clock frequency; see Table 3.

DSP_CLK0

CLK32K(2)

CLK32K output enable/disable. If CLK32K = 0; then the CLK32K output is

enabled. If CLK32K = 1; then the CLK32K output is disabled.

CLK26M(3)

CLK26M output enable/disable. If CLK26M = 0; then the CLK26M output is

enabled. If CLK26M = 1; then the CLK26M output is disabled.

CLK20M

CLK20M output enable/disable. If CLK20M = 0; then the CLK20M output is

enabled. If CLK20M = 1; then the CLK20M output is disabled.

CLK13M

CLK13M output enable/disable. If CLK13M = 0; then the CLK13M output is

enabled. If CLK13M = 1; then the CLK13M output is disabled.

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