PCF5083HSLASH5V2SLASHF3 datasheet(103/136 Pages) PHILIPS

103 / 136 page

1996 Oct 29

103

Philips Semiconductors

Objective speciﬁcation

GSM signal processing IC

PCF5083

Table 80 Bit mask register (Power-Down Control Lines)

Note

1. RSTx = 0 means reset condition if either RSTO or RSTC is asserted; ‘

−’ denotes not affected from reset line.

During reset (RST, RSTO, RSTC) only those registers with an explicitly given reset value are affected. All other

registers are undefined and have to be set by the controller.

Table 81 Quarterbit Counter Control Register

Note

1. RSTx = 0 means reset condition if either RSTO or RSTC is asserted; ‘

−’ denotes not affected from reset line.

During reset (RST, RSTO, RSTC) only those registers with an explicitly given reset value are affected. All other

registers are undefined and have to be set by the controller.

BIT

R/W

SYMBOL

OPERATION (if bit is set)

RST = 0

RSTx=0(1)

R/W

PDRX1

A logic 1 enables the control line. A logic 0 disables the

control line, output level determined with corresponding

output polarity ﬂag

−

R/W

PDRX2

−

R/W

(N)PDTX1,

(N)PDBIAS

−

R/W

NPDTX2

−

R/W

PDSYN

−

R/W

TXKEY1

−

R/W

TXKEY2

−

R/W

RXON

−

R/W

TXON

−

R/W

BEN

−

R/W

GPON1

−

R/W

GPON2

−

R/W

REFON

−

R/W

DSPON

−

R/W

NREFON

−

Bit

R/W

SYMBOL

OPERATION (if bit is set)

RST = 0

RSTx=0(1)

R/W

SYNC

Enable SYNC mode

−

R/W

INSERT

Enable INSERT mode

−

R/W

EXTRACT

Enable EXTRACT mode

−

R/W

SLEEP

Enable Sleep mode

−

R/W

SLEEPRED

Enable Reduced Sleep mode

−

R/W

CAL

Start Sleep mode calibration procedure

−

R/W

FSCEXT

Enable IOM®-2 FSC period extension mode

−

R/W

FSCRED

Enable IOM®-2 FSC period reduction mode

−

PCF5083H/5V2/F3 数据表(PDF) 103 Page - NXP Semiconductors

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