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AS73211 数据表(PDF) 38 Page - OSRAM GmbH

部件名 AS73211
功能描述  XYZ True Color Sensor with I²C Interface
PDF  66 Pages
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制造商  OSRAM [OSRAM GmbH]
网页  http://www.osram.com
标志 OSRAM - OSRAM GmbH

AS73211 数据表(HTML) 38 Page - OSRAM GmbH

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AS73211
Functional Description
Datasheet
• PUBLIC
DS000556
• v3-01 • 2018-Feb-07
65
│ 37
During the measurement cycle within the conversion time TCONV an input signal overdriving must be
avoided, even if it occurs limited in time related to TCONV. In this case, the input light is too much
concerning the chosen irradiance responsivity Re of the AS73211 tolerates. An internal function of the
analog conversion monitors all channels during the conversion process in terms of the relation of input
light and chosen irradiance responsivity Re determined via CREG1:GAIN. In case the input light of at
least one of the channels is too much, the status bit STATUS:ADCOF (see Figure 54) is set to
signalize the problem and the chosen GAIN of the A/D converter (CREG1:GAIN) has to be decreased
for reducing the irradiance responsivity Re of the sensor.
7.14
Divider
For the purpose to expand the measurement ranges, an internal implemented divider or prescaler can
be used to scale the results. This might be necessary if the resolution of the conversion is set to a
value higher than 16 bits. If the digital divider is used the conversion result is downscaled according to:
Equation 4:
MRES
N
FSR
R
MRES
E
DIV
CLK
E
e
DIV
e
e
[dec]
1
[dec]
1
2
2
MRES: Digital output value of the conversion (content of output registers MRES1 to MRES3)
Ee: Input light irradiance regarding to the photodiode’s area within the conversion time interval
FSREe: Full Scale Range of detectable input light irradiance Ee
Re: Irradiance responsivity (see Figure 48)
NCLK: Number of clock cycles within the conversion time interval TCONV (see Figure 48)
2
1+DIV[dec]: V
alue of the divider factor respectively prescaler (CREG2:DIV = 7…0), see Figure 49.
The A/D converters of the AS73211 operate with a resolution of 24 bits, but their results are only
provided as 16-bit wide values. The divider allows to read out the otherwise not available upper 8 bits,
depending on the value of CREG2:DIV, if CREG2:EN_DIV is set to ‚1‘.
Therefore, the divider acts as feature to digitally downscale the converter gain, but with a larger full
scale range (FSR). The effective dynamic range of the device is increased without changing the
conversion time.



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